PIC16F684-ISL

Manufacturer Part NumberPIC16F684-ISL
ManufacturerMicrochip Technology Inc.
PIC16F684-ISL datasheets
 


Specifications of PIC16F684-ISL

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Page 77/164

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11.0
ENHANCED
CAPTURE/COMPARE/PWM
(ECCP) MODULE
The
enhanced
Capture/Compare/PWM
module contains a 16-bit register which can operate as
a:
• 16-bit Capture register
• 16-bit Compare register
• PWM Master/Slave Duty Cycle register
Capture/Compare/PWM
Register
1
comprised of two 8-bit registers: CCPR1L (low byte)
and CCPR1H (high byte).
REGISTER 11-1:
CCP1CON — ENHANCED CCP OPERATION REGISTER (ADDRESS: 15h)
R/W-0
P1M1
bit 7
bit 7-6
P1M<1:0>: PWM Output Configuration bits
If CCP1M<3:2> = 00, 01, 10:
xx = P1A assigned as Capture/Compare input; P1B, P1C, P1D assigned as port pins
If CCP1M<3:2> = 11:
00 = Single output; P1A modulated; P1B, P1C, P1D assigned as port pins
01 = Full-bridge output forward; P1D modulated; P1A active; P1B, P1C inactive
10 = Half-bridge output; P1A, P1B modulated with dead band control; P1C, P1D assigned as
port pins
11 = Full-bridge output reverse; P1B modulated; P1C active; P1A, P1D inactive
bit 5-4
DC1B<1:0>: PWM Duty Cycle Least Significant bits
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L.
bit 3-0
CCP1M<3:0>: ECCP Mode Select bits
0000 = Capture/Compare/PWM off (resets ECCP module)
0001 = Unused (reserved)
0010 = Compare mode, toggle output on match (CCP1IF bit is set)
0011 = Unused (reserved)
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, set output on match (CCP1IF bit is set)
1001 = Compare mode, clear output on match (CCP1IF bit is set)
1010 = Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin
is unaffected)
1011 = Compare mode, trigger special event (CCP1IF bit is set; CCP1 resets TMR1or TMR2,
and starts an A/D conversion, if the A/D module is enabled)
1100 = PWM mode; P1A, P1C active-high; P1B, P1D active-high
1101 = PWM mode; P1A, P1C active-high; P1B, P1D active-low
1110 = PWM mode; P1A, P1C active-low; P1B, P1D active-high
1111 = PWM mode; P1A, P1C active-low; P1B, P1D active-low
Legend:
R = Readable bit
-n = Value at POR
 2004 Microchip Technology Inc.
The CCP1CON register controls the operation of
ECCP. The special event trigger is generated by a
compare match and will clear both TMR1H and TMR1L
registers.
(ECCP)
TABLE 11-1:
ECCP Mode
Capture
Compare
(CCPR1)
is
PWM
R/W-0
R/W-0
R/W-0
R/W-0
P1M0
DC1B1
DC1B0
CCP1M3
W = Writable bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
Preliminary
PIC16F684
ECCP MODE – TIMER
RESOURCES REQUIRED
Timer Resource
Timer1
Timer1
Timer2
R/W-0
R/W-0
R/W-0
CCP1M2
CCP1M1
CCP1M0
bit 0
x = Bit is unknown
DS41202C-page 75