PIC16F684-ISL

Manufacturer Part NumberPIC16F684-ISL
ManufacturerMicrochip Technology Inc.
PIC16F684-ISL datasheets
 


Specifications of PIC16F684-ISL

CaseN/ANotesNEW
Date_code11+  
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
Page 71
72
Page 72
73
Page 73
74
Page 74
75
Page 75
76
Page 76
77
Page 77
78
Page 78
79
Page 79
80
Page 80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
Page 79/164

Download datasheet (3Mb)Embed
PrevNext
11.2
Compare Mode
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RC5/CCP1/P1A pin
is:
• Driven high
• Driven low
• Remains unchanged
The action on the pin is based on the value of control
bits, CCP1M<3:0> (CCP1CON<3:0>). At the same
time, interrupt flag bit, CCP1IF (PIR1<5>), is set.
FIGURE 11-2:
COMPARE MODE
OPERATION BLOCK
DIAGRAM
CCP1CON<3:0>
Mode Select
Set Flag bit CCP1IF
(PIR1<5>)
RC5/CCP1/P1A
CCPR1H CCPR1L
pin
Q
S
Output
Logic
Match
R
TMR1H
TRISC<5>
Output Enable
Special Event Trigger
Special Event Trigger will:
• clear TMR1H and TMR1L registers
• NOT set interrupt flag bit TMR1F (PIR1<0>)
• set the GO/DONE bit (ADCON0<1>)
TABLE 11-2:
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1
Addr
Name
Bit 7
Bit 6
0Bh/
INTCON
GIE
PEIE
8Bh
0Ch
PIR1
EEIF
ADIF
CCP1IF
0Eh
TMR1L
Holding register for the Least Significant Byte of the 16-bit TMR1 register
0Fh
TMR1H
Holding register for the Most Significant Byte of the 16-bit TMR1 register
10h
T1CON
T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu
1Ah
CMCON1
13h
CCPR1L
Capture/Compare/PWM Register 1 Low Byte
14h
CCPR1H
Capture/Compare/PWM Register 1 High Byte
15h
CCP1CON
P1M1
P1M0
DC1B1
87h
TRISC
TRISC5
8Ch
PIE1
EEIE
ADIE
CCP1IE
Legend: — = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Capture,
Compare or Timer1 module.
 2004 Microchip Technology Inc.
11.2.1
CCP1 PIN CONFIGURATION
The user must configure the RC5/CCP1/P1A pin as an
output by clearing the TRISC<5> bit.
Note:
Clearing the CCP1CON register will force
the RC5/CCP1/P1A compare output latch
to the default low level. This is not the
PORTC I/O data latch.
11.2.2
TIMER1 MODE SELECTION
Timer1 must be running in Timer mode or Synchro-
nized Counter mode if the ECCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
11.2.3
SOFTWARE INTERRUPT MODE
When Generate Software Interrupt mode is chosen
(CCP1M<3:0> = 1010), the CCP1 pin is not affected.
The CCP1IF (PIR1<5>) bit is set, causing a ECCP
interrupt (if enabled). See Register 11-1.
11.2.4
SPECIAL EVENT TRIGGER
In this mode (CCP1M<3:0> = 1011), an internal
hardware trigger is generated, which may be used to
Comparator
initiate an action. See Register 11-1.
TMR1L
The special event trigger output of ECCP resets the
TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bit programmable period register for
Timer1. The special event trigger output also starts an
A/D conversion (if the A/D module is enabled).
Note:
The special event trigger from the ECCP
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
Bit 5
Bit 4
Bit 3
Bit 2
T0IE
INTE
RAIE
T0IF
C2IF
C1IF
OSFIF
DC1B0
CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000
TRISC4
TRISC3
TRISC2
C2IE
C1IE
OSFIE
Preliminary
PIC16F684
Value on
Value on
Bit 1
Bit 0
all other
POR, BOD
Resets
INTF
RAIF
0000 0000 0000 0000
TMR2IF
TMR1IF 0000 0000 0000 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
T1GSS
C2SYNC ---- --10 ---- --10
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
TRISC1
TRISC0 --11 1111 --11 1111
TMR2IE
TMR1IE 0000 0000 0000 0000
DS41202C-page 77