PIC16F684-ISL

Manufacturer Part NumberPIC16F684-ISL
ManufacturerMicrochip Technology Inc.
PIC16F684-ISL datasheets
 

Specifications of PIC16F684-ISL

CaseN/ANotesNEW
Date_code11+  
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
Page 81
82
Page 82
83
Page 83
84
Page 84
85
Page 85
86
Page 86
87
Page 87
88
Page 88
89
Page 89
90
Page 90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
Page 83/164

Download datasheet (3Mb)Embed
PrevNext
11.3.4
HALF-BRIDGE MODE
In the Half-bridge Output mode, two pins are used as
outputs to drive push-pull loads. The PWM output sig-
nal is output on the RC5/CCP1/P1A pin, while the com-
plementary PWM output signal is output on the
RC4/C2OUT/P1B pin (Figure 11-6). This mode can be
used for half-bridge applications, as shown in
Figure 11-7, or for full-bridge applications, where four
power switches are being modulated with two PWM
signals.
In Half-bridge Output mode, the programmable dead
band delay can be used to prevent shoot-through
current in half-bridge power devices. The value of bits
PDC<6:0> (PWM1CON<6:0>) sets the number of
instruction cycles before the output is driven active. If
the value is greater than the duty cycle, the corre-
sponding output remains inactive during the entire
cycle. See Section 11.3.6 “Programmable Dead
Band Delay” for more details of the dead band delay
operations.
FIGURE 11-7:
EXAMPLES OF HALF-BRIDGE APPLICATIONS
Standard Half-bridge Circuit (“Push-Pull”)
PIC16F684
Half-bridge Output Driving a Full-bridge Circuit
P1A
PIC16F684
P1B
 2004 Microchip Technology Inc.
Since the P1A and P1B outputs are multiplexed with
the PORTC<5:4> data latches, the TRISC<5:4> bits
must be cleared to configure P1A and P1B as outputs.
FIGURE 11-6:
Period
Duty Cycle
(2)
P1A
td
(2)
P1B
(1)
td = Dead Band Delay
Note 1: At this time, the TMR2 register is equal to the
PR2 register.
2: Output signals are shown as active-high.
V+
FET
Driver
P1A
Load
FET
Driver
P1B
V-
V+
FET
Driver
Load
FET
Driver
V-
Preliminary
PIC16F684
HALF-BRIDGE PWM
OUTPUT
Period
td
(1)
(1)
+
V
-
+
V
-
FET
Driver
FET
Driver
DS41202C-page 81