DP83848IVV+ National Semiconductor, DP83848IVV+ Datasheet

DP83848IVV+

Manufacturer Part Number

DP83848IVV+

Description

Manufacturer

National Semiconductor

Datasheets

1.DP83848IVV.pdf (84 pages)

2.DP83848IVV.pdf (82 pages)

Specifications of DP83848IVV+

Notes

NEW

Date_code

10+

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System Diagram

PHYTER

DP83848I PHYTER

Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver

General Description

The DP83848I is a robust fully featured 10/100 single

port Physical Layer device offering low power con-

sumption, including several intelligent power down

states. These low power modes increase overall prod-

uct reliability due to decreased power dissipation. Sup-

porting multiple intelligent power modes allows the

application to use the absolute minimum amount of

power needed for operation. In addition to low power,

the DP83848I is optimized for cable length perfor-

mance far exceeding IEEE specifications.

The DP83848I includes a 25MHz clock out. This

means that the application can be designed with a

minimum of external parts, which in turn results in the

lowest possible total cost of the solution.

The DP83848I easily interfaces to twisted pair media

via an external transformer and fully supports JTAG

IEEE specification 1149.1 for ease of manufacturing.

Additionally both MII and RMII are supported ensuring

ease and flexibility of design.

The DP83848I features integrated sublayers to sup-

port both 10BASE-T and 100BASE-TX Ethernet proto-

cols, which ensures compatibility and interoperability

with all other standards based Ethernet solutions.

The DP83848I is offered in a small form factor (48 pin

LQFP) so that a minimum of board space is needed.

Applications

• High End Peripheral Devices

• Industrial Controls and Factory Automation

• General Embedded Applications

MPU/CPU

is a registered trademark of National Semiconductor.

MII/RMII/SNI

- Industrial Temperature

Source

25 MHz

Clock

Typical Application

DP83848I

10/100 Mb/s

Features

• Low-power 3.3V, 0.18 m CMOS technology

• Low power consumption < 270mW Typical

• 3.3V MAC Interface

• Auto-MDIX for 10/100 Mb/s

• Energy Detection Mode

• 25 MHz clock out

• SNI Interface (configurable)

• RMII Rev. 1.2 Interface (configurable)

• MII Serial Management Interface (MDC and MDIO)

• IEEE 802.3u MII

• IEEE 802.3u Auto-Negotiation and Parallel Detection

• IEEE 802.3u ENDEC, 10BASE-T transceivers and filters

• IEEE 802.3u PCS, 100BASE-TX transceivers and filters

• IEEE 1149.1 JTAG

• Integrated ANSI X3.263 compliant TP-PMD physical sub-

• Error-free Operation up to 150 meters

• Programmable LED support Link, 10 /100 Mb/s Mode, Activ-

• Single register access for complete PHY status

• 10/100 Mb/s packet BIST (Built in Self Test)

• 48-pin LQFP package (7mm) x (7mm)

layer with adaptive equalization and Baseline Wander com-

pensation

ity, and Collision Detect

Status

LEDs

www.national.com

100BASE-TX

10BASE-T

May 2008

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