HEF4043BT,653 NXP Semiconductors, HEF4043BT,653 Datasheet

IC R/S LATCH 3-STATE QUAD 16SOIC

HEF4043BT,653

Manufacturer Part Number
HEF4043BT,653
Description
IC R/S LATCH 3-STATE QUAD 16SOIC
Manufacturer
NXP Semiconductors
Series
4000Br
Datasheet

Specifications of HEF4043BT,653

Logic Type
S-R Latch
Circuit
1:1
Output Type
Tri-State
Voltage - Supply
3 V ~ 15 V
Independent Circuits
4
Delay Time - Propagation
15ns
Current - Output High, Low
3mA, 3mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
16-SOIC (3.9mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
933372880653
HEF4043BTD-T
HEF4043BTD-T
1. General description
2. Features
3. Applications
4. Ordering information
Table 1.
All types operate from
Type number
HEF4043BP
HEF4043BT
Ordering information
Package
Name
DIP16
SO16
40
The HEF4043B is a quad R/S latch with 3-state outputs with a common output enable
input (OE). Each latch has an active HIGH set input (1S to 4S), an active HIGH reset input
(1R to 4R) and an active HIGH 3-state output (1Q to 4Q).
When OE is HIGH, the latch output (nQ) is determined by the nR and nS inputs as shown
in
does not affect the state of the latch. The high impedance off-state feature allows common
bussing of the outputs.
It operates over a recommended V
(usually ground). Unused inputs must be connected to V
also suitable for use over the industrial (−40 °C to +85 °C) temperature range.
°
Table
C to +85
HEF4043B
Quad R/S latch with 3-state outputs
Rev. 09 — 16 December 2009
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Operates across the full industrial temperature range −40 °C to +85 °C
Complies with JEDEC standard JESD 13-B
Four-bit storage with output enable
Description
plastic dual in-line package; 16 leads (300 mil)
plastic small outline package; 16 leads; body width 3.9 mm
3. When OE is LOW, the latch outputs are in the high impedance OFF-state. OE
°
C.
DD
power supply range of 3 V to 15 V referenced to V
DD
, V
SS
, or another input. It is
Product data sheet
Version
SOT38-4
SOT109-1
SS

Related parts for HEF4043BT,653

HEF4043BT,653 Summary of contents

Page 1

HEF4043B Quad R/S latch with 3-state outputs Rev. 09 — 16 December 2009 1. General description The HEF4043B is a quad R/S latch with 3-state outputs with a common output enable input (OE). Each latch has an active HIGH set ...

Page 2

... NXP Semiconductors 5. Functional diagram 3-STATE OUTPUTS Fig 1. Functional diagram 6. Pinning information 6.1 Pinning Fig 3. Pin configuration HEF4043B_9 Product data sheet 001aae616 Fig 2. Logic diagram for one latch HEF4043B n. 001aae617 Rev. 09 — 16 December 2009 HEF4043B Quad R/S latch with 3-state outputs nS nR ...

Page 3

... NXP Semiconductors 6.2 Pin description Table 2. Pin description Symbol Pin Functional description [1] Table 3. Function table Inputs [ HIGH voltage level LOW voltage level don’t care high impedance state. 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). ...

Page 4

... NXP Semiconductors 9. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter V supply voltage DD V input voltage I T ambient temperature amb Δt/ΔV input transition rise and fall rate 10. Static characteristics Table 6. Static characteristics unless otherwise specified Symbol Parameter V HIGH-level input voltage ...

Page 5

... NXP Semiconductors Table 6. Static characteristics …continued unless otherwise specified Symbol Parameter I supply current DD C input capacitance I 11. Dynamic characteristics Table 7. Dynamic characteristics ° For waveforms and test circuit see SS amb Symbol Parameter Conditions nR → nQ; t HIGH to LOW PHL propagation delay see nS → ...

Page 6

... NXP Semiconductors Table 8. Dynamic power dissipation P P can be calculated from the formulas shown Symbol Parameter dynamic power dissipation 12. Waveforms t and t are the input rise and fall times Logic levels: V and V are typical output voltage levels that occur with the output load. ...

Page 7

... NXP Semiconductors OE input output LOW-to-OFF OFF-to-LOW output HIGH-to-OFF OFF-to-HIGH Measurement points are given in Fig 5. Output enable (OE) to latch output (nQ) enable time (t Table 9. Measurement points Supply voltage Input HEF4043B_9 Product data sheet PLZ PHZ outputs on outputs off Table 9. and t PZL Output 0.5V ...

Page 8

... NXP Semiconductors negative positive a. Input waveform b. Test circuit Test and measurement data is given in Definitions test circuit: DUT = Device Under Test Termination resistance should be equal to output impedance Load capacitance including jig and probe capacitance. L Fig 6. Test circuit for measuring switching times Table 10. ...

Page 9

... NXP Semiconductors 13. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT b max. min. max. 1.73 mm 4.2 0.51 3.2 1.30 0.068 inches 0.17 0.02 0.13 0.051 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...

Page 10

... NXP Semiconductors SO16: plastic small outline package; 16 leads; body width 3 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 11

... NXP Semiconductors 14. Revision history Table 11. Revision history Document ID Release date HEF4043B_9 20091216 • Modifications: Section 12 “Waveforms” Table 10 “Test data” HEF4043B_8 20091127 HEF4043B_7 20090710 HEF4043B_6 20081111 HEF4043B_5 20080729 HEF4043B_4 20080710 HEF4043B_CNV_3 19950101 HEF4043B_CNV_2 19950101 HEF4043B_9 Product data sheet Quad R/S latch with 3-state outputs ...

Page 12

... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 13

... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Functional description . . . . . . . . . . . . . . . . . . . 3 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 14 Revision history ...

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