HEF4043BP,652 NXP Semiconductors, HEF4043BP,652 Datasheet - Page 6

• Manufacturer Part Number: HEF4043BP,652
• Description: IC R/S LATCH 3-STATE QUAD 16DIP
• Manufacturer: NXP Semiconductors
• Series: 4000Br

Specifications of HEF4043BP,652

• Logic Type: S-R Latch
• Circuit: 1:1
• Output Type: Tri-State
• Voltage - Supply: 3 V ~ 15 V
• Independent Circuits: 4
• Delay Time - Propagation: 15ns
• Current - Output High, Low: 3mA, 3mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Package / Case: 16-DIP (0.300", 7.62mm)
• Number Of Circuits: 4
• Logic Family: HEF4000
• Polarity: Non-Inverting
• High Level Output Current: - 3.6 mA
• Low Level Output Current: 32 mA
• Propagation Delay Time: 25 ns at 15 V
• Supply Voltage (max): 15.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: Through Hole
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 933296670652; HEF4043BPN; HEF4043BPN

NXP Semiconductors
Table 8.
P
12. Waveforms
HEF4043B_9
Product data sheet
Symbol
P
D
Fig 4.
D
can be calculated from the formulas shown. V
t
Logic levels: V
Transition times: transition time (t
Measurement points are given in
Input minimum set (nS) and reset (nR) pulse widths, inputs nS or nR to latch output (nQ) propagation
delay and nQ transition time
r
Dynamic power dissipation P
Parameter
dynamic power
dissipation
and t
f
are the input rise and fall times.
OL
and V
OH
V
10 V
15 V
5 V
DD
are typical output voltage levels that occur with the output load.
output nQ
input nR
input nS
t
Table 9
) = HIGH LOW (t
Typical formula for P
P
P
P
D
V
V
D
D
D
0 V
0 V
OH
OL
V
V
= 1100 × f
= 4400 × f
= 11400 × f
I
I
and test data is given in
Rev. 09 — 16 December 2009
10 %
SS
= 0 V; t
10 %
THL
i
V
i
+ Σ(f
90 %
+ Σ(f
i
M
) or LOW HIGH (t
+ Σ(f
t
r
r
t
V
W
= t
90 %
t
M
PLH
o
t
o
TLH
f
o
× C
× C
≤
× C
D
20 ns; T
L
(μW)
L
) × V
) × V
L
t
Table
) × V
f
DD
DD
TLH
amb
DD
V
10.
2
2
M
2
) transition times.
t
W
= 25
t
PHL
t
THL
001aai286
Quad R/S latch with 3-state outputs
°
C.
where:
f
f
C
V
Σ(f
i
o
DD
= input frequency in MHz;
L
= output frequency in MHz;
o
= output load capacitance in pF;
× C
= supply voltage in V;
L
) = sum of the outputs.
HEF4043B
© NXP B.V. 2009. All rights reserved.
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