MC100ELT21DR2 ON Semiconductor, MC100ELT21DR2 Datasheet
MC100ELT21DR2
Manufacturer Part Number
MC100ELT21DR2
Description
Manufacturer
ON Semiconductor
Specifications of MC100ELT21DR2
Date_code
07
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MC10ELT21, MC100ELT21
5 V Differential PECL to
TTL Translator
Description
Because PECL (Positive ECL) levels are used, only +5 V and ground
are required. The small outline 8-lead package and the single gate of
the ELT21 makes it ideal for those applications where space,
performance and low power are at a premium.
this device only. For single-ended input conditions, the unused
differential input is connected to V
V
and V
to 0.5 mA. When not used, V
Features
•
•
•
•
•
•
© Semiconductor Components Industries, LLC, 2008
August, 2008 − Rev. 12
BB
The MC10ELT/100ELT21 is a differential PECL to TTL translator.
The V
The 100 Series contains temperature compensation.
3.5 ns Typical Propagation Delay
24 mA TTL Output
Flow Through Pinouts
Operating Range: V
Q Output Will Default LOW with Inputs Left Open or < 1.3 V
Pb−Free Packages are Available
may also rebias AC coupled inputs. When used, decouple V
CC
BB
via a 0.01 mF capacitor and limit current sourcing or sinking
pin, an internally generated voltage supply, is available to
CC
= 4.75 V to 5.25 V with GND = 0 V
BB
should be left open.
BB
as a switching reference voltage.
1
BB
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
CASE 506AA
MN SUFFIX
CASE 948R
DT SUFFIX
CASE 751
D SUFFIX
H
K
5C
2Q
M
TSSOP−8
*For additional marking information, refer to
8
(Note: Microdot may be in either location)
SOIC−8
Application Note AND8002/D.
DFN8
8
= MC10
= MC100
= MC10
= MC100
= Date Code
1
ORDERING INFORMATION
1
http://onsemi.com
8
1
8
1
MARKING DIAGRAMS*
ALYWG
HT21
A
L
Y
W
G
Publication Order Number:
1
HLT21
ALYW
G
G
4
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
8
1
MC10ELT21/D
8
1
KLT21
ALYW
ALYWG
1
KT21
G
G
4
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