MC74HC373ADTG ON Semiconductor, MC74HC373ADTG Datasheet

MC74HC373ADTG

Manufacturer Part Number

MC74HC373ADTG

Description

IC LATCH TRANSP OCT 3ST 20-TSSOP

Manufacturer

ON Semiconductor

Series

74HCr

Type

D-Typer

Datasheets

1.MC74HC373ANG.pdf (9 pages)

2.MC74HC373ADTG.pdf (10 pages)

Specifications of MC74HC373ADTG

Logic Type

D-Type Transparent Latch

Circuit

8:8

Output Type

Tri-State

Voltage - Supply

2 V ~ 6 V

Independent Circuits

Delay Time - Propagation

21ns

Current - Output High, Low

7.8mA, 7.8mA

Operating Temperature

-55°C ~ 125°C

Mounting Type

Surface Mount

Package / Case

20-TSSOP

Latch Type

Transparent

Output Current

7.8mA

Propagation Delay

21ns

No. Of Bits

Ic Output Type

Tri State Non Inverted

Supply Voltage Range

2V To 6V

Logic Case Style

TSSOP

No. Of Pins

Rohs Compliant

Yes

Number Of Circuits

Logic Family

74HC

Polarity

Non-Inverting

High Level Output Current

- 7.8 mA

Low Level Output Current

32 mA

Propagation Delay Time

125 ns at 2 V, 80 ns at 3 V, 25 ns at 4.5 V, 21 ns at 6 V

Supply Voltage (max)

6 V

Supply Voltage (min)

2 V

Maximum Operating Temperature

+ 125 C

Minimum Operating Temperature

- 55 C

Mounting Style

SMD/SMT

Number Of Bits

Number Of Elements

Latch Mode

Transparent

Technology

CMOS

Package Type

TSSOP

Operating Supply Voltage (typ)

2.5/3.3/5V

Operating Supply Voltage (min)

Operating Supply Voltage (max)

Operating Temp Range

-55C to 125C

Operating Temperature Classification

Military

Mounting

Surface Mount

Pin Count

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

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MC74HC373A

Octal 3-State Non-Inverting

Transparent Latch

High-Performance Silicon-Gate CMOS

inputs are compatible with standard CMOS outputs; with pullup

resistors, they are compatible with LSTTL outputs.

asynchronously) when Latch Enable is high. When Latch Enable goes

low, data meeting the setup and hold time becomes latched.

when Output Enable is high, all device outputs are forced to the

high-impedance state. Thus, data may be latched even when the

outputs are not enabled.

data inputs on the opposite side of the package from the outputs to

facilitate PC board layout.

Features

•

*For additional information on our Pb-Free strategy and soldering details, please

March, 2008 - Rev. 13

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

The MC74HC373A is identical in pinout to the LS373. The device

These latches appear transparent to data (i.e., the outputs change

The Output Enable input does not affect the state of the latches, but

The HC373A is identical in function to the HC573A which has the

The HC373A is the non-inverting version of the HC533A.

Output Drive Capability: 15 LSTTL Loads

Outputs Directly Interface to CMOS, NMOS and TTL

Operating Voltage Range: 2.0 to 6.0 V

Low Input Current: 1.0 mA

High Noise Immunity Characteristic of CMOS Devices

In Compliance with the JEDEC Standard No. 7.0 A Requirements

Chip Complexity: 186 FETs or 46.5 Equivalent Gates

Pb-Free Packages are Available*

See detailed ordering and shipping information in the package

dimensions section on page 3 of this data sheet.

ORDERING INFORMATION

WL, L

YY, Y

WW, W

(Note: Microdot may be in either location)

http://onsemi.com

DW SUFFIX

CASE 751D

CASE 948E

SOEIAJ-20

DT SUFFIX

TSSOP-20

CASE 738

CASE 967

N SUFFIX

F SUFFIX

SOIC-20

PDIP-20

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb-Free Package

Publication Order Number:

DIAGRAMS

MC74HC373AN

MC74HC373A/D

MARKING

AWLYYWWG

AWLYWWG

74HC373A

HC373A

ALYWG

373A

Related parts for MC74HC373ADTG

MC74HC373ADTG Summary of contents

Page 1

... Chip Complexity: 186 FETs or 46.5 Equivalent Gates • Pb-Free Packages are Available* *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2008 March, 2008 - Rev. 13 http://onsemi ...

Page 2

LOGIC DIAGRAM DATA D3 INPUTS LATCH ENABLE 1 OUTPUT ENABLE Î Î Î Î Î Î Î Î Î Î Î Design Criteria Î ...

Page 3

... ORDERING INFORMATION Device MC74HC373AN MC74HC373ANG MC74HC373ADW MC74HC373ADWG MC74HC373ADWR2 MC74HC373ADWR2G MC74HC373ADT MC74HC373ADTG MC74HC373ADTR2 MC74HC373ADTR2G MC74HC373AF MC74HC373AFG MC74HC373AFEL MC74HC373AFELG †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free. ...

Page 4

... Current (per Package) Î Î Î Î Î Î Î Î Î Î Î Î Î NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). AC ELECTRICAL CHARACTERISTICS Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î ...

Page 5

TIMING REQUIREMENTS ( pF, Input ...

Page 6

TEST POINT OUTPUT DEVICE UNDER TEST *Includes all probe and jig capacitance Figure Figure 7. EXPANDED LOGIC DIAGRAM ...

Page 7

SEATING PLANE 20X 0. 18X MC74HC373A PACKAGE DIMENSIONS PDIP-20 N SUFFIX PLASTIC DIP PACKAGE CASE 738-03 ...

Page 8

K 20X REF 0.10 (0.004) 0.15 (0.006 L PIN 1 IDENT 1 0.15 (0.006 - 0.100 (0.004) -T- SEATING PLANE 16X 0.36 MC74HC373A PACKAGE DIMENSIONS TSSOP-20 DT ...

Page 9

... Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada ...

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