MM74HC123AN | |
|---|---|
| Manufacturer Part Number | MM74HC123AN |
| Description | IC MULTIVIBRATOR MONO DL 16-DIP |
| Manufacturer | Fairchild Semiconductor |
| Series | 74HC |
| MM74HC123AN datasheets |
|
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Warranty: 60 days
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Specifications of MM74HC123AN | |||
|---|---|---|---|
| Logic Type | Monostable | Independent Circuits | 2 |
| Schmitt Trigger Input | Yes | Propagation Delay | 22ns |
| Current - Output High, Low | 5.2mA, 5.2mA | Voltage - Supply | 2 V ~ 6 V |
| Operating Temperature | -40°C ~ 85°C | Mounting Type | Through Hole |
| Package / Case | 16-DIP (0.300", 7.62mm) | Elements Per Chip | 2 |
| Logic Family | HC | Input Bias Current (max) | 0.008 mA |
| Propagation Delay Time | 197 ns, 48 ns, 38 ns | High Level Output Current | - 5.2 mA |
| Low Level Output Current | 5.2 mA | Supply Voltage (max) | 6 V |
| Supply Voltage (min) | 2 V | Maximum Operating Temperature | + 85 C |
| Minimum Operating Temperature | - 40 C | Mounting Style | Through Hole |
| Operating Supply Voltage | 2.5 V, 3.3 V, 5 V | Lead Free Status / RoHS Status | Lead free / RoHS Compliant |
| Other names | 74HC123 MM74HC123N | ||
PrevNext
Theory of Operation
1POSITIVE EDGE TRIGGER
2NEGATIVE EDGE TRIGGER
3POSITIVE EDGE TRIGGER
4POSITIVE EDGE RE-TRIGGER (PULSE LENGTHENING)
5RESET PULSE SHORTENING
6CLEAR TRIGGER
TRIGGER OPERATION
As shown in Figure 1 and the logic diagram, before an
input trigger occurs, the one shot is in the quiescent state
with the Q output LOW, and the timing capacitor C
pletely charged to V
. When the trigger input A goes from
CC
V
to GND (while inputs B and clear are held to V
CC
valid trigger is recognized, which turns on comparator C1
and Nchannel transistor N11. At the same time the output
latch is set. With transistor N1 on, the capacitor C
idly discharges toward GND until V
is reached. At this
REF1
point the output of comparator C1 changes state and tran-
sistor N1 turns off. Comparator C1 then turns off while at
the same time comparator C2 turns on. With transistor N1
off, the capacitor C
begins to charge through the timing
EXT
resistor, R
, toward V
. When the voltage across C
EXT
CC
equals V
, comparator C2 changes state causing the
REF2
output latch to reset (Q goes LOW) while at the same time
disabling comparator C2. This ends the timing cycle with
the monostable in the quiescent state, waiting for the next
trigger.
A valid trigger is also recognized when trigger input B goes
from GND to V
(while input A is at GND and input clear
CC
is at V
2). The MM74HC123A can also be triggered when
CC
clear goes from GND to V
(while A is at GND and B is at
CC
V
6).
CC
It should be noted that in the quiescent state C
charged to V
causing the current through resistor R
CC
to be zero. Both comparators are “off” with the total device
current due only to reverse junction leakages. An added
feature of the MM74HC123A is that the output latch is set
via the input trigger without regard to the capacitor voltage.
Thus, propagation delay from trigger to Q is independent of
FIGURE 1.
the value of C
, R
, or the duty cycle of the input
EXT
EXT
waveform.
RETRIGGER OPERATION
com-
EXT
The MM74HC123A is retriggered if a valid trigger occurs 3
followed by another trigger 4 before the Q output has
) a
CC
returned to the quiescent (zero) state. Any retrigger, after
the timing node voltage at the R/C
from V
, but has not yet reached V
rap-
REF1
EXT
increase in output pulse width T. When a valid retrigger is
initiated 4, the voltage at the R/C
V
before progressing along the RC charging curve
REF1
toward V
. The Q output will remain HIGH until time T,
CC
after the last valid retrigger.
Because the trigger-control circuit flip-flop resets shortly
EXT
after C
has discharged to the reference voltage of the
X
lower reference circuit, the minimum retrigger time, t
function of internal propagation delays and the discharge
time of C
:
X
Another removal/retrigger time occurs when a short clear
pulse is used. Upon receipt of a clear, the one shot must
charge the capacitor up to the upper trip point before the
one shot is ready to receive the next trigger. This time is
is fully
EXT
dependent on the capacitor used and is approximately:
EXT
5
pin has begun to rise
EXT
, will cause an
REF2
pin will again drop to
EXT
is a
rr
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