74HCT423D,118 NXP Semiconductors, 74HCT423D,118 Datasheet

IC DUAL RETRIG MULTIVIB 16SOIC

74HCT423D,118

Manufacturer Part Number
74HCT423D,118
Description
IC DUAL RETRIG MULTIVIB 16SOIC
Manufacturer
NXP Semiconductors
Series
74HCTr
Datasheet

Specifications of 74HCT423D,118

Logic Type
Monostable
Independent Circuits
2
Schmitt Trigger Input
Yes
Propagation Delay
22ns
Current - Output High, Low
4mA, 4mA
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
16-SOIC (3.9mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
74HCT423D-T
74HCT423D-T
933715350118
1. General description
2. Features and benefits
74HC423; 74HCT423 are high-speed Si-gate CMOS devices that are pin compatible with
Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC423; 74HCT423 dual retriggerable monostable multivibrator with reset has two
methods of output pulse width control.
The nA and nB inputs’ Schmitt trigger action makes them highly tolerant to slower input
rise and fall times.
The 74HC423; 74HCT423 are identical to the 74HC123; 74HCT123 except that they
cannot be triggered via the reset input.
1. The minimum pulse width is essentially determined by the selection of an external
2. Once triggered, the basic output pulse width may be extended by retriggering the
74HC423; 74HCT423
Dual retriggerable monostable multivibrator with reset
Rev. 4 — 18 March 2011
DC triggered from active HIGH or active LOW inputs
Retriggerable for very long pulses up to 100 % duty factor
Direct reset terminates output pulse
Schmitt-trigger action on all inputs except for the reset input
Complies with JEDEC standard no. 7A
ESD protection:
Specified from −40 °C to +85 °C and from −40 °C to +125 °C
resistor (R
gated active LOW-going edge input (nA) or the active HIGH-going edge input (nB). By
repeating this process, the output pulse period (nQ = HIGH, nQ = LOW) can be made
as long as desired. When nRD is LOW, it forces the nQ output LOW, the nQ output
HIGH and also inhibits the triggering.
by reset.
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
EXT
) and capacitor (C
EXT
), see
Figure 10
Section
and
12.1.
Figure 11
illustrate pulse control
Product data sheet

Related parts for 74HCT423D,118

74HCT423D,118 Summary of contents

Page 1

Dual retriggerable monostable multivibrator with reset Rev. 4 — 18 March 2011 1. General description 74HC423; 74HCT423 are high-speed Si-gate CMOS devices that are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with ...

Page 2

... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name −40 °C to +125 °C 74HC423N 74HCT423N −40 °C to +125 °C 74HC423D 74HCT423D −40 °C to +125 °C 74HC423BQ 74HCT423BQ 74HCT423DB −40 °C to +125 °C 74HCT423PW −40 °C to +125 °C 4 ...

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... NXP Semiconductors 1RD 11 2RD Fig 2. Logic symbol Fig 4. Logic diagram 74HC_HCT423 Product data sheet Dual retriggerable monostable multivibrator with reset 1CEXT 14 2CEXT 6 1REXT/CEXT 15 2REXT/CEXT 001aah797 Fig All information provided in this document is subject to legal disclaimers. Rev. 4 — 18 March 2011 74HC423; 74HCT423 14 CX ...

Page 4

... NXP Semiconductors 5. Pinning information 5.1 Pinning 74HC423 74HCT423 1RD 2CEXT 6 2REXT/CEXT 7 GND 8 001aah785 Fig 5. Pin configuration DIP16, SO16 and (T)SSOP16 5.2 Pin description Table 2. Pin description Symbol 1A, 2A 1B, 2B 1RD, 2RD 1Q, 2Q GND 1Q, 2Q 1CEXT, 2CEXT 1REXT/CEXT, 2REXT/CEXT V CC 74HC_HCT423 Product data sheet ...

Page 5

... NXP Semiconductors 6. Functional description [1] Table 3. Function table Input nRD ↓ HIGH voltage level LOW voltage level don’t care; ↑ = LOW-to-HIGH transition; ↓ = HIGH-to-LOW transition; = one HIGH level output pulse; = one LOW level output pulse. [2] If the monostable multivibrator was triggered before this condition was established, the pulse will continue as programmed. ...

Page 6

... NXP Semiconductors 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC V input voltage I V output voltage O T ambient temperature amb Δt/ΔV input transition rise and fall rate 9. Static characteristics Table 6. Static characteristics At recommended operating conditions ...

Page 7

... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions C input capacitance I 74HCT423 V HIGH-level input voltage V LOW-level input voltage V HIGH-level output voltage V LOW-level output voltage I input leakage current I supply current ΔI additional supply per input pin; V ...

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... NXP Semiconductors 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; test circuit see Figure Symbol Parameter Conditions 74HC423 t propagation nQ delay pF; see EXT nRD nQ; see transition time see Figure pulse width nA input LOW; see input HIGH; see nRD input LOW; see HIGH or nQ LOW kΩ ...

Page 9

... NXP Semiconductors Table 7. Dynamic characteristics GND = 0 V; test circuit see Figure Symbol Parameter Conditions R external timing V = 2.0 V; see EXT CC resistor external timing V = 5.0 V; see EXT CC capacitor C power per package dissipation capacitance 74HCT423 t propagation nQ delay pF; see EXT nRD nQ pF; see EXT ...

Page 10

... NXP Semiconductors Table 7. Dynamic characteristics GND = 0 V; test circuit see Figure Symbol Parameter Conditions C power per package dissipation capacitance [ the same as t and PHL PLH [ the same as t and THL TLH [3] For other R and C combinations see EXT EXT = K × R × (typ.), where: ...

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... NXP Semiconductors 11. Waveforms input V M GND input GND V I nRD input GND t PLH output PHL output Measurement points are given in V and V are typical voltage output levels that occur with the output load Fig 7. Pulse widths, propagation delays from inputs (nA, nB, nRD) to outputs (nQ, nQ) and output transition times Table 8 ...

Page 12

... NXP Semiconductors (ns ° 5.0 V and T CC amb ( 100 kΩ. EXT ( kΩ. EXT ( kΩ. EXT ( kΩ. EXT Fig 8. Typical output pulse width as a function of the external capacitor values nB input nA input nQ output nRD = HIGH. Fig 10. Output pulse control using retrigger pulse (t 74HC_HCT423 Product data sheet ...

Page 13

... NXP Semiconductors nB input nRD input nQ output nA = LOW. Fig 11. Output pulse control using reset input nRD Test data is given in Table Definitions for test circuit Termination resistance should be equal to output impedance Load capacitance including jig and probe capacitance. L Fig 12. Test circuit for measuring switching times Table 9 ...

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... NXP Semiconductors 12. Application information 12.1 Timing component connections The basic output pulse width is essentially determined by the values of the external timing components R (1) For minimum noise generation it is recommended that the nCEXT pins (6, 14) are connected to ground externally to the GND pin (8). ...

Page 15

... NXP Semiconductors Fig 14. Power-up output pulse elimination circuit 12.3 Power-down considerations A large capacitor C the capacitor’s stored energy. When a system containing this device is powered-down or a rapid decrease of V capacitor discharging through the input protection diodes. To avoid this possibility, use a damping diode D large current surges and connect as shown in Fig 15 ...

Page 16

... NXP Semiconductors 13. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. mm 4.2 0.51 3.2 inches 0.17 0.02 0.13 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...

Page 17

... NXP Semiconductors SO16: plastic small outline package; 16 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 18

... NXP Semiconductors DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 x 3.5 x 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

Page 19

... NXP Semiconductors SSOP16: plastic shrink small outline package; 16 leads; body width 5 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT338-1 Fig 19. Package outline SOT338-1 (SSOP16) ...

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... NXP Semiconductors TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

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... Figure 4 updated (errata). Product data sheet • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Section 3 “Ordering information”, Section 5 “Pinning information” and Section 13 “ ...

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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...

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... NXP Semiconductors Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 17. Contact information For more information, please visit: For sales office addresses, please send an email to: 74HC_HCT423 Product data sheet Dual retriggerable monostable multivibrator with reset 16 ...

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... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional description . . . . . . . . . . . . . . . . . . . 5 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 12 Application information ...

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