IDT74FCT388915T133

Manufacturer Part NumberIDT74FCT388915T133
ManufacturerIntegrated Device Technology, Inc.
IDT74FCT388915T133 datasheet
 

Specifications of IDT74FCT388915T133

CasePLCC/28Date_code00+
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IDT54/74FCT388915T 70/100/133/150
3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER
TEST CIRCUITS AND WAVEFORMS
50 TO V
/2, CL = 20PF
CC
V
CC
V
IN
Pulse
D.U.T.
Generator
R
T
PROPAGATION DELAY, OUTPUT SKEW
SYNC INPUT
(SYNC (1) or
SYNC (0))
t
PD
FEEDBACK
INPUT
Q/2 OUTPUT
t
SKEWf
t
SKEWALL
Q0-Q4
OUTPUTS
Q5 OUTPUT
2Q OUTPUT
(These waveforms represent the configuration of Figure 3a)
NOTES:
1. The FCT388915T aligns rising edges of the FEEDBACK input and SYNC input, therefore the SYNC input does not require a 50% duty cycle.
2. All skew specs are measured between the V
around a center point.
3. If a Q ouput is connected to the FEEDBACK input (this situation is not shown), the Q output frequency would match the SYNC input frequency, the 2Q
output would run at twice the SYNC frequency and the Q/2 output would run at half the SYNC frequency.
ENABLE AND DISABLE TIMES
ENABLE
CONTROL
INPUT
t
PZL
3V
OUTPUT
SWITCH
NORMALLY
1.5V
6V
LOW
t
t
PZH
PHZ
OUTPUT
SWITCH
NORMALLY
1.5V
GND
HIGH
0V
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH
2. Pulse Generator for All Pulses: t
2.5ns; t
F
ENABLE AND DISABLE TEST CIRCUIT
V
CC
100
V
OUT
Pulse
20pF
Generator
100
C
L
3052 drw 05
t
CYCLE
SYNC INPUT
t
t
SKEWr
SKEWf
t
CYCLE
"Q" OUTPUTS
/2 crossing point of the appropriate output edges. All skews are specified as "windows", not as deviation
CC
SWITCH POSITION
DISABLE
3V
1.5V
0V
t
PLZ
3V
DEFINITIONS:
0.3V
V
OL
C
= Load capacitance: includes jig and probe capacitance.
L
R
= Termination resistance: should be equal to Z
T
V
OH
Generator.
0.3V
0V
3052 drw 07
2.5ns
R
9.8
MILITARY AND COMMERCIAL TEMPERATURE RANGES
V
CC
V
V
OUT
IN
D.U.T.
R
T
1.5V
V
CC/2
V
CC/2
t
SKEWr
V
CC/2
1.5V
V
CC/2
3052 drw 08
Test
Switch
Disable Low
6V
Enable Low
Disable High
GND
Enable High
OUT
6.0V
GND
500
500
3052 drw 06
3052 tbl 10
of the Pulse
10