IDT74FCT388915T133

Manufacturer Part NumberIDT74FCT388915T133
ManufacturerIntegrated Device Technology, Inc.
IDT74FCT388915T133 datasheet
 

Specifications of IDT74FCT388915T133

CasePLCC/28Date_code00+
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IDT54/74FCT388915T 70/100/133/150
3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER
PIN CONFIGURATIONS
4
3
2
1
FEEDBK
5
REF_SEL
6
SYNC(0)
7
J28-1,
V
(AN)
8
CC
L28-1
LF
9
GND(AN)
10
SYNC(1)
11
12
13
14
15
PLCC/LCC
TOP VIEW
PIN DESCRIPTION
Pin Name
I/O
SYNC(0)
I
SYNC(1)
I
REF_SEL
I
FREQ_SEL
I
FEEDBACK
I
LF
I
Q0-Q4
O
Q5
O
2Q
O
Q/2
O
LOCK
O
RST
OE/
I
PLL_EN
I
28
27
26
25
Q/2
24
GND
FEEDBACK
23
Q3
22
V
CC
21
Q2
20
GND
19
LOCK
FREQ_SEL
16
17
18
3052 drw 02
Reference clock input.
Reference clock input.
Chooses reference between SYNC (0) & SYNC (1). (Refer to functional block diagram).
Selects between
1 and
2 frequency options. (Refer to functional block diagram).
Feedback input to phase detector.
Input for external loop filter connection.
Clock output.
Inverted clock output.
Clock output (2 x Q frequency).
Clock output (Q frequency
2).
Indicates phase lock has been achieved (HIGH when locked).
Asynchronous reset (active LOW) and output enable (active HIGH). When HIGH, outputs are
enabled. When LOW, outputs are in HIGH impedance.
Disables phase-lock for low frequency testing. (Refer to functional block diagram).
9.8
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1
28
GND
Q4
2
27
Q5
V
3
26
V
2Q
CC
OE/RST
4
25
Q/2
5
24
GND
6
23
REF_SEL
Q3
7
SYNC(0)
22
V
SO28-7
8
V
(AN)
21
Q2
CC
9
20
LF
GND
GND(AN)
10
19
LOCK
11
18
SYNC(1)
PLL_EN
12
17
GND
GND
13
16
Q1
14
15
V
Q0
SSOP
TOP VIEW
Description
CC
CC
CC
3052 drw 03
3052 tbl 01
2