IDT74FCT388915T133

Manufacturer Part NumberIDT74FCT388915T133
ManufacturerIntegrated Device Technology, Inc.
IDT74FCT388915T133 datasheet
 

Specifications of IDT74FCT388915T133

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IDT54/74FCT388915T 70/100/133/150
3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
I
Quiescent Power Supply Current
CC
TTL Inputs HIGH
I
Dynamic Power Supply
CCD
(4)
Current
C
Power Dissipation Capacitance
PD
I
Total Power Supply Current
C
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
= 3.3V, +25 C ambient.
CC
3. Per TTL driven input. All other inputs at V
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. It is derived with Q frequency as the reference.
5. Values for these conditions are examples of the I
6. I
= I
+ I
+ I
C
QUIESCENT
INPUTS
DYNAMIC
I
= I
+ I
D
N
+ I
(f) + I
C
CC
CC
H
T
CCD
LOAD
,
I
= Quiescent Current (I
I
and I
CC
CCL
CCH
I
= Power Supply Current for a TTL High Input (V
CC
D
= Duty Cycle for TTL Inputs High
H
N
= Number of TTL Inputs at D
T
H
I
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
CCD
f =2Q Frequency
I
= Dynamic Current due to load.
LOAD
SYNC INPUT TIMING REQUIREMENTS
Symbol
Parameter
Min.
T
Rise/Fall Times,
RISE/FALL
SYNC inputs
(0.8V to 2.0V)
Frequency Input Frequency,
10.0
SYNC Inputs
Duty Cycle Input Duty Cycle,
25%
SYNC Inputs
OUTPUT FREQUENCY SPECIFICATIONS
Symbol
Parameter
f2Q
Operating frequency 2Q Output
fQ
Operating frequency Q0-Q4,
fQ/2
Operating frequency Q/2 Output
NOTES:
1. Note 7 in "General AC Specification Notes" and Figure 3 describes this specification and its actual limits depending on the feedback connection.
2. Maximum operating frequency is guaranteed with the part in a phase locked condition and all outputs loaded.
Test Conditions
V
= Max.
V
CC
(3)
V
= V
–2.1V
IN
CC
V
= Max.
V
CC
All Outputs Open
V
50% Duty Cycle
(6)
V
= Max.
CC
PLL_EN = 1, LOCK = 1, FEEDBACK = Q4
SYNC frequency = 50MHz. All bits loaded with
15pF
V
= Max.
CC
PLL_EN = 1, LOCK = 1, FEEDBACK = Q4
SYNC frequency = 50MHz. All bits loaded with
50 Thevenin termination and 20pF
or GND.
CC
formula. These limits are guaranteed but not tested.
CC
)
CCZ
= 3.4V)
IN
Max.
Unit
3.0
ns
(1)
2Q fmax
MHz
75%
3052 tbl 06
Min.
40
Q
5 Outputs
20
10
9.8
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(1)
(2)
Min.
Typ.
(3)
= V
–0.6V
2.0
IN
CC
= V
0.2
IN
CC
= GND
IN
15
30
90
(2)
Max.
70
100
133
150
70
100
133
150
35
50
66.7
75
17.5
25
33.3
37.5
Max.
Unit
30
A
0.3
mA/
MHz
25
pF
60
mA
120
mA
3052 tbl 05
Unit
MHz
MHz
MHz
3052 tbl 07
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