IDT74FCT388915T133

Manufacturer Part NumberIDT74FCT388915T133
ManufacturerIntegrated Device Technology, Inc.
IDT74FCT388915T133 datasheet
 

Specifications of IDT74FCT388915T133

CasePLCC/28Date_code00+
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IDT54/74FCT388915T 70/100/133/150
3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER
The frequency relationship shown here is applicable to all Q
outputs (Q0, Q1, Q2, Q3 and Q4).
1:2 INPUT TO "Q" OUTPUT FREQUENCY RELATION-
SHIP
In this application, the Q/2 output is connected to the
FEEDBACK input. The internal PLL will line up the positive
edges of Q/2 and SYNC, thus the Q/2 frequency will equal the
SYNC frequency. The Q outputs (Q0-Q4,
at 2X the Q/2 frequency, and the 2Q output will run at 4X the
Q/2 frequency.
12.5 MHz feedback signal
HIGH
Q4
OE/RST
Q5
FEEDBACK
LOW
REF_SEL
12.5 MHz
SYNC(0)
input
FCT388915T
V
(AN)
CC
LF
GND(AN)
FQ_SEL
Q0
Q1
HIGH
Allowable Input Frequency Range:
10MHz to ( f2Q MAX Spec)/4 (for FREQ_SEL HIGH)
5MHz to (f2Q MAX Spec)/8 (for FREQ_SEL LOW)
Figure 3a. Wiring Diagram and Frequency Relationships With Q/2
Output Feedback
1:1 INPUT TO "Q" OUTPUT FREQUENCY RELATION-
SHIP
In this application, the Q4 output is connected to the
FEEDBACK input. The internal PLL will line up the positive
edges of Q4 and SYNC, thus the Q4 frequency (and the rest
of the "Q" outputs) will equal the SYNC frequency. The Q/2
output will always run at 1/2 the Q frequency, and the 2Q
output will run at 2X the Q frequency.
25 MHz feedback signal
LOW
Q5
25 MHz
) will always run
input
50 MHz signal
2Q
Q/2
Allowable Input Frequency Range:
25 MHz
Q3
"Q"
20MHz to (f2Q MAX Spec)/2 (for FREQ_SEL HIGH)
Clock
10MHz to (f2Q MAX Spec)/4 (for FREQ_SEL LOW)
Outputs
Figure 3b. Wiring Diagram and Frequency Relationships With Q4
Q2
2:1 INPUT TO "Q" OUTPUT FREQUENCY RELATION-
SHIP
PLL_EN
In this application, the 2Q output is connected to the
FEEDBACK input. The internal PLL will line up the positive
HIGH
edges of 2Q and SYNC, thus the 2Q frequency will equal the
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SYNC frequency. The Q/2 output will always run at 1/4 the
2Q frequency, and the Q output will run at 1/2 the 2Q
frequency.
LOW
50 MHz
input
Allowable Input Frequency Range:
40MHz to (f2Q MAX Spec) (for FREQ_SEL HIGH)
20MHz to (f2Q MAX Spec)/2 (for FREQ_SEL LOW)
Figure 3c. Wiring Diagram and Frequency Relationships With 2Q
9.8
MILITARY AND COMMERCIAL TEMPERATURE RANGES
50 MHz signal
HIGH
2Q
Q4
OE/RST
Q5
FEEDBACK
Q/2
REF_SEL
SYNC(0)
Q3
V
(AN)
FCT388915T
CC
LF
Q2
GND(AN)
FQ_SEL
Q0
Q1
PLL_EN
HIGH
HIGH
Output Feedback
50 MHz feedback signal
HIGH
Q4
2Q
OE/RST
Q5
FEEDBACK
Q/2
REF_SEL
SYNC(0)
Q3
FCT388915T
V
(AN)
CC
Q2
LF
GND(AN)
FQ_SEL
PLL_EN
Q0
Q1
HIGH
HIGH
Output Feedback
12.5 MHz
signal
25 MHz
"Q"
Clock
Outputs
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12.5 MHz
input
25 MHz
"Q"
Clock
Outputs
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