IDT74FCT388915T133

Manufacturer Part NumberIDT74FCT388915T133
ManufacturerIntegrated Device Technology, Inc.
IDT74FCT388915T133 datasheet
 

Specifications of IDT74FCT388915T133

CasePLCC/28Date_code00+
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IDT54/74FCT388915T 70/100/133/150
3.3V LOW SKEW PLL-BASED CLOCK DRIVER
CLOCK
@f
SYSTEM
CLOCK
SOURCE
DISTRIBUTE
CLOCK @f
CLOCK @2f
at point of use
Figure 4. Multiprocessing Application Using the FCT388915T for Frequency Multiplication
FCT388915T System Level Testing Functionality
When the PLL_EN pin is LOW, the PLL is bypassed and the
FCT388915T is in low frequency "test mode". In test mode
(with FREQ_SEL HIGH), the 2Q output is inverted from the
selected SYNC input, and the Q outputs are divide-by-2
(negative edge triggered) of the SYNC input, and the Q/2
output is divide-by-4 (negative edge triggered).
FREQ_SEL LOW the 2Q output is divide-by-2 of the SYNC,
the Q outputs divide-by-4, and the Q/2 output divide-by-8.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CMMU
CMMU
FCT388915T
PLL
CPU
CMMU
2f
CMMU
CMMU
CMMU
CMMU
FCT388915T
PLL
CPU
CMMU
2f
CMMU
CMMU
FCT388915T
PLL
MEMORY
2f
CONTROL
MEMORY
CARDS
CLOCK @2f
at point of use
and Low Board-to-Board skew
These relationships can be seen in the block diagram. A
recommended test configuration would be to use SYNC0 or
SYNC1 as the test clock input, and tie PLL_EN and REF_SEL
together and connect them to the test select logic.
This functionality is needed since most board-level testers
With
run at 1 MHz or below, and theFCT 388915T cannot lock onto
that low of an input frequency. In the test mode described
above, any test frequency test can be used.
9.8
CPU
CARD
CPU
CARD
3052 drw 13
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