74AHC164D,118 NXP Semiconductors, 74AHC164D,118 Datasheet

74AHC164D,118
Manufacturer Part Number	74AHC164D,118
Description	IC 8BIT SRLIN/PAROUT REG 14SOIC
Manufacturer	NXP Semiconductors
Series	74AHC
74AHC164D,118 datasheets	1. 74AHC164D118.pdf (18 pages)

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Specifications of 74AHC164D,118
Package / Case	14-SOIC (3.9mm Width), 14-SOL	Logic Type	Shift Register
Function	Serial to Parallel	Output Type	Standard
Number Of Elements	1	Number Of Bits Per Element	8
Voltage - Supply	2 V ~ 5.5 V	Operating Temperature	-40°C ~ 125°C
Mounting Type	Surface Mount	Counting Sequence	Serial to Parallel
Number Of Circuits	1	Logic Family	AHC
Propagation Delay Time	4.5 ns	Supply Voltage (max)	5.5 V
Maximum Operating Temperature	+ 125 C	Minimum Operating Temperature	- 40 C
Mounting Style	SMD/SMT	Supply Voltage (min)	2 V
Lead Free Status / RoHS Status	Lead free / RoHS Compliant	Other names	74AHC164D-T 74AHC164D-T 935265465118

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74AHC164; 74AHCT164

8-bit serial-in/parallel-out shift register

Rev. 03 — 24 April 2008

1. General description

The 74AHC164; 74AHCT164 shift register is a high-speed Si-gate CMOS device and is

pin compatible with Low-power Schottky TTL (LSTTL). It is speciﬁed in compliance with

JEDEC standard No. 7A.

The 74AHC164; 74AHCT164 input signals are 8-bit serial through one of two inputs (DSA

or DSB); either input can be used as an active HIGH enable for data entry through the

other input. Both inputs must be connected together or an unused input must be tied

HIGH.

Data shifts one place to the right on each LOW-to-HIGH transition of the clock input (CP)

and enters into output Q0, which is a logical AND of the two data inputs (DSA and DSB)

that existed one set-up time prior to the rising clock edge.

A LOW-level on the master reset (MR) input overrides all other inputs and clears the

2. Features

Balanced propagation delays

All inputs have Schmitt-trigger actions

Inputs accept voltages higher than V

Input levels:

For 74AHC164: CMOS level

For 74AHCT164: TTL level

ESD protection:

HBM EIA/JESD22-A114E exceeds 2000 V

MM EIA/JESD22-A115-A exceeds 200 V

CDM EIA/JESD22-C101C exceeds 1000 V

Multiple package options

Speciﬁed from 40 C to +85 C and from 40 C to +125 C

Product data sheet

Download datasheet (103Kb)

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74AHC164D,118 Summary of contents
Page 1 Rev. 03 — 24 April 2008 1. General description The 74AHC164; 74AHCT164 shift register is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL speciﬁed in compliance ... Page 2 ... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 74AHC164 74AHC164D +125 C 74AHC164PW +125 C 74AHC164BQ +125 C 74AHCT164 74AHCT164D +125 C 74AHCT164PW +125 C 74AHCT164BQ +125 C 4. Functional diagram Fig 1. Functional diagram 74AHC_AHCT164_3 Product data sheet 74AHC164; 74AHCT164 Description SO14 plastic small outline package ... Page 3 ... NXP Semiconductors DSA 1 2 DSB 001aac423 Fig 2. Logic symbol DSA DSB FF1 Fig 4. Logic diagram 74AHC_AHCT164_3 Product data sheet 74AHC164; 74AHCT164 Fig FF2 FF3 FF4 Rev. 03 — 24 April 2008 8-bit serial-in/parallel-out shift register SRG8 8 C1 & 001aac424 IEC logic symbol FF5 ... Page 4 ... NXP Semiconductors 5. Pinning information 5.1 Pinning DSA 1 2 DSB Q0 3 164 GND 001aac422 Fig 5. Pin conﬁguration SO14 and TSSOP14 5.2 Pin description Table 2. Pin description Symbol Pin DSA 1 DSB GND 74AHC_AHCT164_3 Product data sheet 74AHC164; 74AHCT164 (1) The die substrate is attached to this pad using Fig 6 ... Page 5 ... NXP Semiconductors 6. Functional description [1] Table 3. Function table Operating mode Control MR Reset (clear) L Shift H [ HIGH voltage level HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition LOW voltage level LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition; ... Page 6 ... NXP Semiconductors 8. Recommended operating conditions Table 5. Operating conditions Symbol Parameter 74AHC164 V supply voltage CC V input voltage I V output voltage O T ambient temperature amb t/ V input transition rise and fall rate 74AHCT164 V supply voltage CC V input voltage I V output voltage O T ambient temperature ... Page 7 ... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions I input leakage GND current 5 supply current 5 input I capacitance 74AHCT164 V HIGH-level input voltage V LOW-level input voltage V HIGH-level output voltage 8 LOW-level output voltage ... Page 8 ... NXP Semiconductors 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions 74AHC164 t propagation CP to Qn; see pd delay Qn; see maximum see Figure 7 max frequency pulse width CP HIGH or LOW; ... Page 9 ... NXP Semiconductors Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions t recovery MR to CP; see rec time power MHz dissipation capacitance 74AHCT164 4 5 propagation CP to Qn; see pd delay Qn; see maximum see Figure 7 max frequency ... Page 10 ... NXP Semiconductors 11. Waveforms CP input Qn output Measurement points are given in V and V are typical voltage output levels that occur with the output load Fig 7. Clock pulse width, maximum frequency and input to output propagation delays MR input CP input Qn output Measurement points are given in V and V are typical voltage output levels that occur with the output load ... Page 11 ... NXP Semiconductors CP input DSA, DSB input Qn output Measurement points are given in The shaded areas indicate when the input is permitted to change for predictable output performance. V and V are typical voltage output levels that occur with the output load Fig 9. Data set-up and hold times Table 8 ... Page 12 ... NXP Semiconductors Test data is given in Table Deﬁnitions test circuit Termination resistance should be equal to output impedance Load capacitance including jig and probe capacitance L Fig 10. Load circuitry for measuring switching times Table 9. Test data Type Input V I 74AHC164 V CC 74AHCT164 3.0 V 74AHC_AHCT164_3 Product data sheet ... Page 13 ... NXP Semiconductors 12. Package outline SO14: plastic small outline package; 14 leads; body width 3 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.01 0.069 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ... Page 14 ... NXP Semiconductors TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ... Page 15 ... NXP Semiconductors DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ... Page 16 ... NXP Semiconductors 13. Abbreviations Table 10. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date 74AHC_AHCT164_3 20080424 • Modiﬁcations: Table ... Page 17 ... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation speciﬁcations and product descriptions, at any time and without notice ... Page 18 ... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional description . . . . . . . . . . . . . . . . . . . 5 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16 14 Revision history ...

74AHC164D,118 Summary of contents

Page 1
Rev. 03 — 24 April 2008 1. General description The 74AHC164; 74AHCT164 shift register is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL speciﬁed in compliance ...
Page 2
... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 74AHC164 74AHC164D +125 C 74AHC164PW +125 C 74AHC164BQ +125 C 74AHCT164 74AHCT164D +125 C 74AHCT164PW +125 C 74AHCT164BQ +125 C 4. Functional diagram Fig 1. Functional diagram 74AHC_AHCT164_3 Product data sheet 74AHC164; 74AHCT164 Description SO14 plastic small outline package ...
Page 3
... NXP Semiconductors DSA 1 2 DSB 001aac423 Fig 2. Logic symbol DSA DSB FF1 Fig 4. Logic diagram 74AHC_AHCT164_3 Product data sheet 74AHC164; 74AHCT164 Fig FF2 FF3 FF4 Rev. 03 — 24 April 2008 8-bit serial-in/parallel-out shift register SRG8 8 C1 & 001aac424 IEC logic symbol FF5 ...
Page 4
... NXP Semiconductors 5. Pinning information 5.1 Pinning DSA 1 2 DSB Q0 3 164 GND 001aac422 Fig 5. Pin conﬁguration SO14 and TSSOP14 5.2 Pin description Table 2. Pin description Symbol Pin DSA 1 DSB GND 74AHC_AHCT164_3 Product data sheet 74AHC164; 74AHCT164 (1) The die substrate is attached to this pad using Fig 6 ...
Page 5
... NXP Semiconductors 6. Functional description [1] Table 3. Function table Operating mode Control MR Reset (clear) L Shift H [ HIGH voltage level HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition LOW voltage level LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition; ...
Page 6
... NXP Semiconductors 8. Recommended operating conditions Table 5. Operating conditions Symbol Parameter 74AHC164 V supply voltage CC V input voltage I V output voltage O T ambient temperature amb t/ V input transition rise and fall rate 74AHCT164 V supply voltage CC V input voltage I V output voltage O T ambient temperature ...
Page 7
... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions I input leakage GND current 5 supply current 5 input I capacitance 74AHCT164 V HIGH-level input voltage V LOW-level input voltage V HIGH-level output voltage 8 LOW-level output voltage ...
Page 8
... NXP Semiconductors 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions 74AHC164 t propagation CP to Qn; see pd delay Qn; see maximum see Figure 7 max frequency pulse width CP HIGH or LOW; ...
Page 9
... NXP Semiconductors Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions t recovery MR to CP; see rec time power MHz dissipation capacitance 74AHCT164 4 5 propagation CP to Qn; see pd delay Qn; see maximum see Figure 7 max frequency ...
Page 10
... NXP Semiconductors 11. Waveforms CP input Qn output Measurement points are given in V and V are typical voltage output levels that occur with the output load Fig 7. Clock pulse width, maximum frequency and input to output propagation delays MR input CP input Qn output Measurement points are given in V and V are typical voltage output levels that occur with the output load ...
Page 11
... NXP Semiconductors CP input DSA, DSB input Qn output Measurement points are given in The shaded areas indicate when the input is permitted to change for predictable output performance. V and V are typical voltage output levels that occur with the output load Fig 9. Data set-up and hold times Table 8 ...
Page 12
... NXP Semiconductors Test data is given in Table Deﬁnitions test circuit Termination resistance should be equal to output impedance Load capacitance including jig and probe capacitance L Fig 10. Load circuitry for measuring switching times Table 9. Test data Type Input V I 74AHC164 V CC 74AHCT164 3.0 V 74AHC_AHCT164_3 Product data sheet ...
Page 13
... NXP Semiconductors 12. Package outline SO14: plastic small outline package; 14 leads; body width 3 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.01 0.069 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
Page 14
... NXP Semiconductors TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
Page 15
... NXP Semiconductors DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
Page 16
... NXP Semiconductors 13. Abbreviations Table 10. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date 74AHC_AHCT164_3 20080424 • Modiﬁcations: Table ...
Page 17
... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation speciﬁcations and product descriptions, at any time and without notice ...
Page 18
... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional description . . . . . . . . . . . . . . . . . . . 5 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16 14 Revision history ...

74AHC164D,118

74AHC164D,118

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74AHC164D,118 Summary of contents

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