IC 8BIT SRL SHFT REGISTER 16SOIC

 

74AHC595D,112

Manufacturer Part Number74AHC595D,112
DescriptionIC 8BIT SRL SHFT REGISTER 16SOIC
ManufacturerNXP Semiconductors
Series74AHC
74AHC595D,112 datasheets

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Specifications of 74AHC595D,112

Logic TypeShift RegisterOutput TypeStandard
Number Of Elements1Number Of Bits Per Element8
FunctionSerial to ParallelVoltage - Supply2 V ~ 5.5 V
Operating Temperature-40°C ~ 125°CMounting TypeSurface Mount
Package / Case16-SOIC (3.9mm Width)Lead Free Status / RoHS StatusLead free / RoHS Compliant
Other names74AHC595D
74AHC595D
935265567112		  
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74AHC595; 74AHCT595
8-bit serial-in/serial-out or parallel-out shift register with
output latches; 3-state
Rev. 04 — 11 August 2009
1. General description
The 74AHC595; 74AHCT595 are high-speed Si-gate CMOS devices and are pin
compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with
JEDEC standard No. 7A.
The 74AHC595; 74AHCT595 are 8-stage serial shift registers with a storage register and
3-state outputs. The registers have separate clocks.
Data is shifted on the positive-going transitions of the shift register clock input (SHCP).
The data in each register is transferred to the storage register on a positive-going
transition of the storage register clock input (STCP). If both clocks are connected together,
the shift register will always be one clock pulse ahead of the storage register.
The shift register has a serial input (DS) and a serial standard output (Q7S) for cascading.
It is also provided with asynchronous reset (active LOW) for all 8 shift register stages. The
storage register has 8 parallel 3-state bus driver outputs. Data in the storage register
appears at the output whenever the output enable input (OE) is LOW.
2. Features
I
Balanced propagation delays
I
All inputs have Schmitt-trigger action
I
Inputs accept voltages higher than V
I
Input levels:
N
The 74AHC595 operates with CMOS input levels
N
The 74AHCT595 operates with TTL input levels
I
ESD protection:
N
HBM JESD22-A114E exceeds 2000 V
N
MM JESD22-A115-A exceeds 200 V
N
CDM JESD22-C101C exceeds 1000 V
I
Multiple package options
I
Specified from 40 C to +85 C and from 40 C to +125 C
3. Applications
I
Serial-to-parallel data conversion
I
Remote control holding register
Product data sheet
CC

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74AHC595D,112 Summary of contents

  • Page 1

    Rev. 04 — 11 August 2009 1. General description The 74AHC595; 74AHCT595 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are ...

  • Page 2

    ... NXP Semiconductors 4. Ordering information Table 1. Ordering information Type number Package Temperature range 74AHC595 74AHC595D +125 C 74AHC595PW +125 C 74AHC595BQ +125 C 74AHCT595 74AHCT595D +125 C 74AHCT595PW +125 C 74AHCT595BQ +125 C 5. Functional diagram Fig 1. Functional diagram 74AHC_AHCT595_4 Product data sheet 74AHC595; 74AHCT595 8-bit serial-in/serial-out or parallel-out shift register with output latches ...

  • Page 3

    ... NXP Semiconductors Fig 2. Logic symbol STAGE LATCH Fig 4. Logic diagram 74AHC_AHCT595_4 Product data sheet 8-bit serial-in/serial-out or parallel-out shift register with output latches mna552 Fig 3. STAGES FF0 Rev. 04 — 11 August 2009 74AHC595; 74AHCT595 13 EN3 SRG8 mna553 IEC logic symbol STAGE FF7 ...

  • Page 4

    ... NXP Semiconductors 6. Pinning information 6.1 Pinning 74AHC595 74AHCT595 GND Fig 5. Pin configuration SO16 and TSSOP16 6.2 Pin description Table 2. Pin description Symbol Pin GND 8 Q7S SHCP 11 STCP 74AHC_AHCT595_4 Product data sheet 8-bit serial-in/serial-out or parallel-out shift register with output latches STCP ...

  • Page 5

    ... NXP Semiconductors 7. Functional description [1] Table 3. Function table Control Input SHCP STCP [ HIGH voltage state LOW voltage state; = LOW-to-HIGH transition don’t care change high-impedance OFF-state Fig 7. Timing diagram 74AHC_AHCT595_4 Product data sheet 74AHC595; 74AHCT595 8-bit serial-in/serial-out or parallel-out shift register with output latches ...

  • Page 6

    ... NXP Semiconductors 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC V input voltage I I input clamping current IK I output clamping current OK I output current O I supply current ...

  • Page 7

    ... NXP Semiconductors 10. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 74AHC595 V HIGH-level input voltage LOW-level input voltage HIGH-level output voltage 4.0 mA 8.0 mA LOW-level output voltage 4.0 mA 8.0 mA input leakage GND ...

  • Page 8

    ... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions I input leakage GND current 5 OFF-state output current other inputs supply current 5 additional per input pin supply current other inputs input I capacitance 74AHC_AHCT595_4 Product data sheet 8-bit serial-in/serial-out or parallel-out shift register with output latches … ...

  • Page 9

    ... NXP Semiconductors 11. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions 74AHC595 t propagation SHCP to Q7S; see pd delay STCP to Qn; see Q7S; see enable time OE to Qn; see ...

  • Page 10

    ... NXP Semiconductors Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions f maximum SHCP or STCP; max frequency see Figure pulse width SHCP HIGH or LOW; W see Figure STCP HIGH or LOW; see Figure ...

  • Page 11

    ... NXP Semiconductors Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions t enable time OE to Qn; see disable time OE to Qn; see dis maximum SHCP and STCP; max frequency see Figure 8 t pulse width SHCP HIGH or LOW; ...

  • Page 12

    ... NXP Semiconductors 12. Waveforms SH CP input output Measurement points are given in V and V are typical output voltage levels that occur with the output load Fig 8. Shift clock pulse, maximum frequency and input to output propagation delays SH CP input ST CP input Q n output Measurement points are given in ...

  • Page 13

    ... NXP Semiconductors SH CP input D S input output Measurement points are given in The shaded areas indicate when the input is permitted to change for predictable output performance. V and V are typical output voltage levels that occur with the output load Fig 10. Data set-up and hold times ...

  • Page 14

    ... NXP Semiconductors OE input output LOW-to-OFF OFF-to-LOW output HIGH-to-OFF OFF-to-HIGH Measurement points are given in V and V are typical output voltage levels that occur with the output load Fig 12. Enable and disable times Table 8. Measurement points Type Input V 74AHC595 0.5V 74AHCT595 1.5 V 74AHC_AHCT595_4 Product data sheet 74AHC595 ...

  • Page 15

    ... NXP Semiconductors negative positive Test data is given in Table Definitions for test circuit load capacitance including jig and probe capacitance load resistance termination resistance should be equal to the output impedance test selection switch. Fig 13. Load circuitry for switching times Table 9. Test data Type ...

  • Page 16

    ... NXP Semiconductors 13. Package outline SO16: plastic small outline package; 16 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

  • Page 17

    ... NXP Semiconductors TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

  • Page 18

    ... NXP Semiconductors DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 x 3.5 x 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

  • Page 19

    ... NXP Semiconductors 14. Abbreviations Table 10. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 15. Revision history Table 11. Revision history Document ID Release date 74AHC_AHCT595_4 20090811 • Modifications: Added type number 74AHCT595BQ (DHVQFN16 package) ...

  • Page 20

    ... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

  • Page 21

    ... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Functional description . . . . . . . . . . . . . . . . . . . 5 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16 14 Abbreviations ...

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