74HC166PW,112 NXP Semiconductors, 74HC166PW,112 Datasheet - Page 2

• Manufacturer Part Number: 74HC166PW,112
• Description: IC 8BIT SHIFT REGISTER 16TSSOP
• Manufacturer: NXP Semiconductors
• Series: 74HCr

Specifications of 74HC166PW,112

• Logic Type: Shift Register
• Output Type: Standard
• Number Of Elements: 1
• Number Of Bits Per Element: 8
• Function: Parallel or Serial to Serial
• Voltage - Supply: 2 V ~ 6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 74HC166PW; 74HC166PW; 935188960112

Philips Semiconductors
FEATURES
GENERAL DESCRIPTION
The 74HC/HCT166 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT166 are 8-bit shift registers which have a
fully synchronous serial or parallel data entry selected by
QUICK REFERENCE DATA
GND = 0 V; T
Notes
1. C
2. For HC the condition is V
ORDERING INFORMATION
See
December 1990
SYMBOL
t
f
C
C
PHL
max
Synchronous parallel-to-serial applications
Synchronous serial data input for easy expansion
Clock enable for “do nothing” mode
Asynchronous master reset
For asynchronous parallel data load see “165”
Output capability: standard
I
8-bit parallel-in/serial-out shift register
I
PD
CC
f
f
C
V
For HCT the condition is V
i
o
“74HC/HCT/HCU/HCMOS Logic Package Information”
/ t
CC
PD
= input frequency in MHz
L
category: MSI
= output frequency in MHz
(C
PLH
= output load capacitance in pF
P
= supply voltage in V
is used to determine the dynamic power dissipation (P
L
D
= C
V
amb
CC
PD
PARAMETER
propagation delay
maximum clock frequency
input capacitance
power dissipation capacitance per package
CP to Q
MR to Q
2
= 25 C; t
V
f
o
CC
) = sum of outputs
2
7
7
f
r
i
= t
I
I
f
= GND to V
= GND to V
= 6 ns
(C
L
V
CC
2
CC
CC
f
o
) where:
1.5 V
2
.
CONDITIONS
C
notes 1 and 2
an active LOW parallel enable (PE) input. When PE is
LOW one set-up time prior to the LOW-to-HIGH clock
transition, parallel data is entered into the register. When
PE is HIGH, data is entered into the internal bit position Q
from serial data input (D
shifted one place to the right (Q
each positive-going clock transition.
This feature allows parallel-to-serial converter expansion
by tying the Q
stage.
The clock input is a gated-OR structure which allows one
input to be used as an active LOW clock enable (CE) input.
The pin assignment for the CP and CE inputs is arbitrary
and can be reversed for layout convenience. The
LOW-to-HIGH transition of input CE should only take place
while CP is HIGH for predictable operation. A LOW on the
master reset (MR) input overrides all other inputs and
clears the register asynchronously, forcing all bit positions
to a LOW state.
L
D
= 15 pF; V
in W):
CC
7
output to the D
= 5 V
s
), and the remaining bits are
HC
15
14
63
3.5
41
s
0
input of the succeeding
74HC/HCT166
TYPICAL
Product specification
Q
1
HCT
20
19
50
3.5
41
Q
2
, etc.) with
UNIT
ns
ns
MHz
pF
pF
0