ADSP2115KP-66 Analog Devices, ADSP2115KP-66 Datasheet

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ADSP2115KP-66

Manufacturer Part Number
ADSP2115KP-66
Description
Manufacturer
Analog Devices
Datasheet

Specifications of ADSP2115KP-66

Case
PLCC
a
GENERAL DESCRIPTION
The ADSP-2100 Family processors are single-chip micro-
computers optimized for digital signal processing (DSP)
and other high speed numeric processing applications. The
ADSP-21xx processors are all built upon a common core. Each
processor combines the core DSP architecture—computation
units, data address generators, and program sequencer—with
differentiating features such as on-chip program and data
memory RAM, a programmable timer, one or two serial ports,
and, on the ADSP-2111, a host interface port.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
SUMMARY
16-Bit Fixed-Point DSP Microprocessors with
Enhanced Harvard Architecture for Three-Bus
Independent Computation Units: ALU, Multiplier/
Single-Cycle Instruction Execution & Multifunction
On-Chip Program Memory RAM or ROM
Integrated I/O Peripherals: Serial Ports, Timer,
FEATURES
25 MIPS, 40 ns Maximum Instruction Rate
Separate On-Chip Buses for Program and Data Memory
Program Memory Stores Both Instructions and Data
Dual Data Address Generators with Modulo and
Efficient Program Sequencing with Zero-Overhead
Automatic Booting of On-Chip Program Memory from
Double-Buffered Serial Ports with Companding Hardware,
ADSP-2111 Host Interface Port Provides Easy Interface
Automatic Booting of ADSP-2111 Program Memory
Three Edge- or Level-Sensitive Interrupts
Low Power IDLE Instruction
PGA, PLCC, PQFP, and TQFP Packages
MIL-STD-883B Versions Available
On-Chip Memory
Performance: Instruction Bus & Dual Data Buses
Accumulator, and Shifter
Instructions
& Data Memory RAM
Host Interface Port (ADSP-2111 Only)
(Three-Bus Performance)
Bit-Reverse Addressing
Looping: Single-Cycle Loop Setup
Byte-Wide External Memory (e.g., EPROM )
Automatic Data Buffering, and Multichannel Operation
to 68000, 80C51, ADSP-21xx, Etc.
Through Host Interface Port
This data sheet describes the following ADSP-2100 Family
processors:
ADSP-2101
ADSP-2103
ADSP-2105
ADSP-2111
ADSP-2115
ADSP-2161/62/63/64 Custom ROM-programmed DSPs
The following ADSP-2100 Family processors are not included
in this data sheet:
ADSP-2100A
ADSP-2165/66
ADSP-21msp5x
ADSP-2171
ADSP-2181
Refer to the individual data sheet of each of these processors for
further information.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
DATA ADDRESS
GENERATORS
DAG 1
ALU
ARITHMETIC UNITS
ADSP-2100 CORE
DAG 2
MAC
SHIFTER
FUNCTIONAL BLOCK DIAGRAM
SEQUENCER
PROGRAM
PROGRAM MEMORY DATA
DATA MEMORY DATA
DATA MEMORY ADDRESS
PROGRAM MEMORY ADDRESS
DSP Microcomputers
with powerdown and larger on-chip
memories (12K Program Memory ROM,
1K Program Memory RAM, 4K Data
Memory RAM)
integrated on-chip A/D and D/A plus
powerdown
Family processor with host interface port,
powerdown, and instruction set extensions
for bit manipulation, multiplication, biased
rounding, and global interrupt masking
features plus 80K bytes of on-chip RAM
configured as 16K words of program
memory and 16K words of data memory.
3.3 V Version of ADSP-2101
Low Cost DSP
DSP with Host Interface Port
DSP Microprocessor
ROM-programmed ADSP-216x processors
Mixed-Signal DSP Processors with
Speed and feature enhanced ADSP-2100
ADSP-21xx processor with ADSP-2171
ADSP-2100 Family
SPORT 0
SERIAL PORTS
PROGRAM
MEMORY
SPORT 1
MEMORY
ADSP-21xx
MEMORY
© Analog Devices, Inc., 1996
DATA
TIMER
Fax: 617/326-8703
(ADSP-2111)
INTERFACE
(ADSP-2111)
HOST
PORT
FLAGS
EXTERNAL
ADDRESS
EXTERNAL
DATA
BUS
BUS

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