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- Integrated Circuits (ICs)/
- Logic - Shift Registers/
CD74HCT597MTE4
CD74HCT597MTE4 | |
|---|---|
| Manufacturer Part Number | CD74HCT597MTE4 |
| Description | IC SHIFT REGISTER 8BIT HS 16SOIC |
| Manufacturer | Texas Instruments |
| Series | 74HCT |
| CD74HCT597MTE4 datasheets |
|
Availability: By request
International delivery:
Warranty: 60 days
×
- We provide standard 60-days warranty for all parts. If warranty differs we always mention it beforehand. In case of return we cover shipping costs.
- If you still have any questions - please contact us
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Shipping terms
- Standard delivery time differs from 5-8 business days if the supplier is a local one to 12-14 days if the suplier is from overseas. If delivery time differs it's always mentioned in our quotation.
- We ship worldwide using main international couriers like FedEx, DHL, UPS, TNT, EMS. We can also use client's freight account. Other shipping methods can be discussed. We do best to meet your needs!
Payment terms
- For new client payment term is payment in advance. At this moment we accept 3 payment methods: wire transfer, PayPal and Western Union. Credit card payment is under constrution and will be introduced soon. Escrow service is acceptable. Net terms for regular customers is not a problem. Working with us is totally safe for you.
- If you still have any questions - please contact us
Specifications of CD74HCT597MTE4 | |||
|---|---|---|---|
| Logic Type | Shift Register | Output Type | Standard |
| Number Of Elements | 1 | Number Of Bits Per Element | 8 |
| Function | Parallel to Serial | Voltage - Supply | 4.5 V ~ 5.5 V |
| Operating Temperature | -55°C ~ 125°C | Mounting Type | Surface Mount |
| Package / Case | 16-SOIC (3.9mm Width) | Lead Free Status / RoHS Status | Lead free / RoHS Compliant |
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CD54HC597, CD74HC597, CD74HCT597
Functional Diagram
ST
SH
CP
CP
X
X
No Clock Edge
X
X
X
X
X
X
H = High Voltage Level, L = Low Voltage Level, X = Don’t Care,
DS
14
15
D0
1
D1
2
D2
3
PARALLEL
D3
8-BIT
DATA
8 F/F
4
D4
SHIFT
INPUTS
STORAGE
REG.
REG.
5
D5
6
D6
7
D7
12
ST
CP
11
SH
CP
13
PL
10
MR
FUNCTION TABLE
PL
MR
X
X
Data Loaded to Input Flip-Flops
L
H
Data Loaded from Inputs to Shift Register
L
H
Data Transferred from Input Flip-Flops to Shift Register
L
L
Invalid Logic, State of Shift Register Indeterminate when
Signals Removed
H
L
Shift Register Cleared
H
H
Shift Register Clocked Qn = Qn-1, Q0 = D
= Transition from Low to High CP Level
2
9
Q7
FUNCTION
S
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