MC14517B
Dual 64−Bit Static Shift
Register
identical, independent, 64−bit registers. Each register has separate clock
and write enable inputs, as well as outputs at bits 16, 32, 48, and 64. Data
at the data input is entered by clocking, regardless of the state of the write
enable input. An output is disabled (open circuited) when the write enable
input is high. During this time, data appearing at the data input as well as
the 16−bit, 32−bit, and 48−bit taps may be entered into the device by
application of a clock pulse. This feature permits the register to be loaded
with 64 bits in 16 clock periods, and also permits bus logic to be used.
This device is useful in time delay circuits, temporary memory storage
circuits, and other serial shift register applications.
Features
•
•
•
•
•
•
•
•
•
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating: Plastic “P and D/DW”
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
to the range V
(e.g., either V
*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting
MAXIMUM RATINGS
© Semiconductor Components Industries, LLC, 2006
June, 2006 − Rev. 6
Techniques Reference Manual, SOLDERRM/D.
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
Input or Output Current (DC or Transient)
per Pin
Power Dissipation per Package (Note 1)
Operating Temperature Range
Storage Temperature Range
Lead Temperature (8−Second Soldering)
The MC14517B dual 64−bit static shift register consists of two
This device contains protection circuitry to guard against damage due to high
Unused inputs must always be tied to an appropriate logic voltage level
Clock Input
Pulses
Schottky TTL Load Over the Rated Temperature Range
Diode Protection on All Inputs
Fully Static Operation
Output Transitions Occur on the Rising Edge of the Clock Pulse
Exceedingly Slow Input Transition Rates May Be Applied to the
3−State Output at 64th−Bit Allows Use in Bus Logic Applications
Shift Registers of any Length may be Fully Loaded with 16 Clock
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low−Power TTL Loads or One Low−Power
Pb−Free Packages are Available*
Packages: – 7.0 mW/_C From 65_C To 125_C
SS
SS
or V
Parameter
v (V
DD
in
). Unused outputs must be left open.
or V
(Voltages Referenced to V
out
) v V
DD
.
Symbol
V
in
I
in
in
V
T
P
and V
, V
, I
T
T
DD
stg
D
A
L
out
out
SS
out
)
−0.5 to +18.0
should be constrained
−55 to +125
−65 to +150
−0.5 to V
Value
+ 0.5
± 10
500
260
DD
1
Unit
mW
mA
°C
°C
°C
V
V
†For information on tape and reel specifications,
MC14517BCP
MC14517BCPG
MC14517BDW
MC14517BDWG
MC14517BDWR2
MC14517BDWR2G
A
WL, L = Wafer Lot
YY, Y
WW, W = Work Week
G
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
1
Device
1
= Assembly Location
= Year
= Pb−Free Package
ORDERING INFORMATION
Q16
Q48
Q64
Q32
WE
V
C
D
PIN ASSIGNMENT
SS
http://onsemi.com
A
A
A
A
A
A
A
DW SUFFIX
CASE 751G
CASE 648
P SUFFIX
SOIC−16
PDIP−16
1
2
3
4
5
6
7
8
(Pb−Free)
(Pb−Free)
(Pb−Free)
SOIC−16
PDIP−16
PDIP−16
SOIC−16
SOIC−16
SOIC−16
Package
Publication Order Number:
16
15
14
13
12
10
11
16
9
1
16
1
1000/Tape & Reel
1000/Tape & Reel
Q16
V
Q48
WE
C
Q64
Q32
D
MC14516BCP
DD
B
B
DIAGRAMS
AWLYYWWG
25 Units/Rail
25 Units/Rail
MARKING
Shipping
AWLYYWWG
B
B
B
B
B
MC14517B/D
47/Rail
47/Rail
14517B
†