R5F562N8BDFP#V0 Renesas Electronics Corporation., R5F562N8BDFP#V0 Datasheet

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R5F562N8BDFP#V0

Manufacturer Part Number
R5F562N8BDFP#V0
Description
QFP 100
Manufacturer
Renesas Electronics Corporation.
Datasheet

Specifications of R5F562N8BDFP#V0

Pack_quantity
1
Comm_code
85423190
Lead_time
126

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R5F562N8BDFP#V0
0
RX62N Group, RX621 Group
RENESAS 32-Bit MCU
100 MHz 32-bit RX MCU with FPU, 165 DMIPS, up to 512-Kbyte Flash,
Ethernet, USB 2.0 Full-Speed Host/Function/OTG, CAN, 12-bit ADC, TFT-LCD,
RTC, up to 14 communication channels
R01DS0052EJ0130 Rev.1.30
2012.01.11
Features
■32-bit RX CPU Core
■Low Power Design and Architecture
■Main Flash Memory, no Wait-State
■Data Flash Memory
■SRAM, no Wait-State
■DMA
■Reset and Supply Management
■System Clocking with Clock Monitoring
■Real Time Clock
■Two Independent Watchdog Timers
 Delivers 165 DMIPS at a maximum operating frequency of
 Single Precision 32-bit IEEE-754 Floating Point
 Accumulator: 32 × 32 to 64-bit result, one instruction
 Mult/Divide Unit, 32 × 32 Multiply in one CPU clock for
 Interrupt response in as few as 5 CPU clock cycles
 CISC-Harvard Architecture with 5-stage pipeline
 Variable length instructions, ultra compact code
 Supports the Memory Protection Unit (MPU)
 Background JTAG debug plus high-speed trace
 2.7V to 3.6V operation from a single supply
 480 µA/MHz Run Mode with all peripherals on
 Deep Software Standby Mode with RTC
 Four low power modes
 100 MHz operation, 10 nsec read cycle
 No wait states for read at full CPU speed
 256K, 384K, 512K Byte size options
 For Instructions or Operands
 Programming from USB, SCI, JTAG, user code
 Up to 32K Bytes with 30K Erase Cycles
 Background Erase/Program does not stall CPU
 64K or 96K Byte size options
 For Operands or Instructions
 Back-up retention in Deep Software Standby Mode
 Four fully programmable internal DMA channels
 Two EXDMA channels for external-to-external transfers
 Data Transfer Controller (DTC)
 Power-On Reset (POR) monitor/generator
 Low Voltage Detect (LVD) with precision setting
 External crystal, 8 MHz to 14 MHz to Internal PLL
 PLL source to system, USB, and Ethernet
 Internal 125 kHz LOCO for IWDT
 External crystal, 32 kHz for RTC
 Full calendar function, BCD format
 125-kHz LOCO operation
100 MHz
multiple instructions
■Up to 14 Communication Interfaces
■External Address Space
■TFT-LCD up to WQVGA resolution
■Up to 20 Extended Function Timers
■1-MHz ADC units with two combination choices
■10-bit DAC, 2 channels
■Up to 128 GPIO
■Operation Temp
 USB 2.0 Full-Speed interfaces with PHY (2ch)
 Ethernet MAC 10/100 Mbps, Half or Full Duplex Supported.
 CAN ISO11898-1, supports 32 mailboxes (1ch)
 SCI channels: Asynchronous, clock sync, smartcard, and 9-
 RSPI (2ch)
 Eight CS areas (8 × 16 Mbytes)
 128-Mbyte SDRAM area
 8-/16-/32-bit bus space selectable for each area
 16-bit MTU2
 8-bit TMR (4ch)
 16-bit CMT (4ch)
 12-bit × 8 ch. unit with single sample/hold circuit
 or (2) 10-bit × 4 ch units each with a sample/hold circuit
 AD-converted value addition mode (12-bit A/D converter)
 5V tolerant, Open-Drain, Internal Pull-up
LQFP100 14×14mm, 0.5mm pitch
LQFP144 20×20mm, 0.5mm pitch
Supports Host/Function/OTG
10 endpoints for types: Control, Interrupt, Bulk, Isochronous
(1ch)
Dedicated DMA with 2-Kbyte transmit and receive FIFOs.
RMII or MII interface to external PHY
bit modes (6ch)
Input capture, Output Compare, PWM output, phase count
mode (12ch)
I
–40°C to +85°C
2
C interfaces up to 1M bps, SMBus support (2ch)
DatasheetDatasheet
TFLGA85 7×7mm, 0.65mm pitch
TFLGA145 9×9mm, 0.65mm pitch
LFBGA176 13×13mm, 0.8mm pitch
R01DS0052EJ0130
Page 1 of 147
2012.01.11
Rev.1.30

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