MT29F8G08ADADAH4-IT:D Micron Semiconductor Products, MT29F8G08ADADAH4-IT:D Datasheet - Page 7

• Manufacturer Part Number: MT29F8G08ADADAH4-IT:D
• Manufacturer: Micron Semiconductor Products

Specifications of MT29F8G08ADADAH4-IT:D

• Pack_quantity: 1000
• Comm_code: 85423269
• Lead_time: 56
• Eccn: 3A991B1A

Micron Confidential and Proprietary
4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory
Features
Figure 51: READ FOR INTERNAL DATA MOVE (00h–35h) with RANDOM DATA READ (05h–E0h) ..................... 80
Figure 52: INTERNAL DATA MOVE (85h-10h) with Internal ECC Enabled ........................................................ 81
Figure 53: INTERNAL DATA MOVE (85h-10h) with RANDOM DATA INPUT with Internal ECC Enabled ............ 81
Figure 54: PROGRAM FOR INTERNAL DATA MOVE (85h–10h) Operation ........................................................ 81
Figure 55: PROGRAM FOR INTERNAL DATA MOVE (85h-10h) with RANDOM DATA INPUT (85h) .................... 82
Figure 56: PROGRAM FOR INTERNAL DATA MOVE TWO-PLANE (85h-11h) Operation .................................... 82
Figure 57: Flash Array Protected: Invert Area Bit = 0 ........................................................................................ 84
Figure 58: Flash Array Protected: Invert Area Bit = 1 ........................................................................................ 84
Figure 59: UNLOCK Operation ....................................................................................................................... 85
Figure 60: LOCK Operation ............................................................................................................................ 86
Figure 61: LOCK TIGHT Operation ................................................................................................................. 87
Figure 62: PROGRAM/ERASE Issued to Locked Block ...................................................................................... 88
Figure 63: BLOCK LOCK READ STATUS .......................................................................................................... 88
Figure 64: BLOCK LOCK Flowchart ................................................................................................................ 89
Figure 65: OTP DATA PROGRAM (After Entering OTP Operation Mode) ........................................................... 92
Figure 66: OTP DATA PROGRAM Operation with RANDOM DATA INPUT (After Entering OTP Operation Mode) ... 93
Figure 67: OTP DATA PROTECT Operation (After Entering OTP Protect Mode) ................................................. 94
Figure 68: OTP DATA READ ........................................................................................................................... 95
Figure 69: OTP DATA READ with RANDOM DATA READ Operation ................................................................. 96
Figure 70: TWO-PLANE PAGE READ .............................................................................................................. 98
Figure 71: TWO-PLANE PAGE READ with RANDOM DATA READ .................................................................... 99
Figure 72: TWO-PLANE PROGRAM PAGE ....................................................................................................... 99
Figure 73: TWO-PLANE PROGRAM PAGE with RANDOM DATA INPUT .......................................................... 100
Figure 74: TWO-PLANE PROGRAM PAGE CACHE MODE ............................................................................... 101
Figure 75: TWO-PLANE INTERNAL DATA MOVE ........................................................................................... 102
Figure 76: TWO-PLANE INTERNAL DATA MOVE with TWO-PLANE RANDOM DATA READ ............................ 103
Figure 77: TWO-PLANE INTERNAL DATA MOVE with RANDOM DATA INPUT ............................................... 104
Figure 78: TWO-PLANE BLOCK ERASE ......................................................................................................... 105
Figure 79: TWO-PLANE/MULTIPLE-DIE READ STATUS Cycle ........................................................................ 105
Figure 80: Spare Area Mapping (x8) ............................................................................................................... 109
Figure 81: Spare Area Mapping (x16) ............................................................................................................. 110
Figure 82: RESET Operation .......................................................................................................................... 119
Figure 83: READ STATUS Cycle ..................................................................................................................... 119
Figure 84: READ STATUS ENHANCED Cycle .................................................................................................. 120
Figure 85: READ PARAMETER PAGE ............................................................................................................. 120
Figure 86: READ PAGE .................................................................................................................................. 121
Figure 87: READ PAGE Operation with CE# “Don’t Care” ............................................................................... 122
Figure 88: RANDOM DATA READ .................................................................................................................. 123
Figure 89: READ PAGE CACHE SEQUENTIAL ................................................................................................ 124
Figure 90: READ PAGE CACHE RANDOM ...................................................................................................... 125
Figure 91: READ ID Operation ...................................................................................................................... 126
Figure 92: PROGRAM PAGE Operation .......................................................................................................... 126
Figure 93: PROGRAM PAGE Operation with CE# “Don’t Care” ........................................................................ 127
Figure 94: PROGRAM PAGE Operation with RANDOM DATA INPUT .............................................................. 127
Figure 95: PROGRAM PAGE CACHE .............................................................................................................. 128
Figure 96: PROGRAM PAGE CACHE Ending on 15h ........................................................................................ 128
Figure 97: INTERNAL DATA MOVE ............................................................................................................... 129
Figure 98: INTERNAL DATA MOVE (85h-10h) with Internal ECC Enabled ....................................................... 129
Figure 99: INTERNAL DATA MOVE (85h-10h) with Random Data Input with Internal ECC Enabled ................. 130
Figure 100: ERASE BLOCK Operation ............................................................................................................ 130
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m60a_4gb_nand.pdf – Rev. J 9/11 EN
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