MT47H256M8EB-25EIT:C Micron Semiconductor Products, MT47H256M8EB-25EIT:C Datasheet - Page 7

• Manufacturer Part Number: MT47H256M8EB-25EIT:C
• Manufacturer: Micron Semiconductor Products

Specifications of MT47H256M8EB-25EIT:C

• Pack_quantity: 171
• Comm_code: 85423239
• Lead_time: 56
• Eccn: EAR99

2Gb: x4, x8, x16 DDR2 SDRAM
Features
Figure 51: READ-to-PRECHARGE – BL = 4 ...................................................................................................... 98
Figure 52: READ-to-PRECHARGE – BL = 8 ...................................................................................................... 98
Figure 53: Bank Read – Without Auto Precharge ............................................................................................. 100
Figure 54: Bank Read – with Auto Precharge .................................................................................................. 101
t
t
Figure 55: x4, x8 Data Output Timing –
DQSQ,
QH, and Data Valid Window .................................................. 102
t
t
Figure 56: x16 Data Output Timing –
DQSQ,
QH, and Data Valid Window ..................................................... 103
t
t
Figure 57: Data Output Timing –
AC and
DQSCK ......................................................................................... 104
Figure 58: Write Burst ................................................................................................................................... 106
Figure 59: Consecutive WRITE-to-WRITE ...................................................................................................... 107
Figure 60: Nonconsecutive WRITE-to-WRITE ................................................................................................ 107
Figure 61: WRITE Interrupted by WRITE ....................................................................................................... 108
Figure 62: WRITE-to-READ ........................................................................................................................... 109
Figure 63: WRITE-to-PRECHARGE ................................................................................................................ 110
Figure 64: Bank Write – Without Auto Precharge ............................................................................................ 111
Figure 65: Bank Write – with Auto Precharge .................................................................................................. 112
Figure 66: WRITE – DM Operation ................................................................................................................ 113
Figure 67: Data Input Timing ........................................................................................................................ 114
Figure 68: Refresh Mode ............................................................................................................................... 115
Figure 69: Self Refresh .................................................................................................................................. 117
Figure 70: Power-Down ................................................................................................................................ 119
Figure 71: READ-to-Power-Down or Self Refresh Entry .................................................................................. 121
Figure 72: READ with Auto Precharge-to-Power-Down or Self Refresh Entry ................................................... 121
Figure 73: WRITE-to-Power-Down or Self Refresh Entry ................................................................................. 122
Figure 74: WRITE with Auto Precharge-to-Power-Down or Self Refresh Entry .................................................. 122
Figure 75: REFRESH Command-to-Power-Down Entry .................................................................................. 123
Figure 76: ACTIVATE Command-to-Power-Down Entry ................................................................................. 123
Figure 77: PRECHARGE Command-to-Power-Down Entry ............................................................................. 124
Figure 78: LOAD MODE Command-to-Power-Down Entry ............................................................................. 124
Figure 79: Input Clock Frequency Change During Precharge Power-Down Mode ............................................ 125
Figure 80: RESET Function ........................................................................................................................... 127
Figure 81: ODT Timing for Entering and Exiting Power-Down Mode ............................................................... 129
Figure 82: Timing for MRS Command to ODT Update Delay .......................................................................... 130
Figure 83: ODT Timing for Active or Fast-Exit Power-Down Mode .................................................................. 130
Figure 84: ODT Timing for Slow-Exit or Precharge Power-Down Modes .......................................................... 131
Figure 85: ODT Turn-Off Timings When Entering Power-Down Mode ............................................................ 131
Figure 86: ODT Turn-On Timing When Entering Power-Down Mode .............................................................. 132
Figure 87: ODT Turn-Off Timing When Exiting Power-Down Mode ................................................................ 133
Figure 88: ODT Turn-On Timing When Exiting Power-Down Mode ................................................................. 134
PDF: 09005aef824f87b6
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2Gb_DDR2.pdf – Rev. H 10/11 EN