SN74LVC1G27DSFR

Manufacturer Part NumberSN74LVC1G27DSFR
Description
ManufacturerTexas Instruments, Inc.
SN74LVC1G27DSFR datasheet
 


Specifications of SN74LVC1G27DSFR

Pack_quantity5000Comm_code85423990
Lead_time42EccnEAR99
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FEATURES
Available in the Texas Instruments
NanoFree™ Package
Supports 5-V V
Operation
CC
Inputs Accept Voltages to 5.5 V
Max t
of 4.5 ns at 3.3 V
pd
Low Power Consumption, 10- A Max I
24-mA Output Drive at 3.3 V
DBV PACKAGE
(TOP VIEW)
A
1
GND
2
B
3
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
The SN74LVC1G27 performs the Boolean function Y = A + B + C or Y = A
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using I
preventing damaging current backflow through the device when it is powered down.
T
PACKAGE
A
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP
(Pb-free)
–40 C to 85 C
SOT (SOT-23) – DBV
SOT (SC-70) – DCK
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SINGLE 3-INPUT POSITIVE-NOR GATE
SCES488D – SEPTEMBER 2003 – REVISED JANUARY 2007
I
Supports Partial-Power-Down Mode
off
Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
CC
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DCK PACKAGE
(TOP VIEW)
A
6
1
C
6
GND
2
5
V
5
CC
B
3
4
Y
4
ORDERING INFORMATION
(1)
ORDERABLE PART NUMBER
Reel of 3000
SN74LVC1G27YZPR
Reel of 3000
SN74LVC1G27DBVR
Reel of 3000
SN74LVC1G27DCKR
SN74LVC1G27
YZP PACKAGE
(BOTTOM VIEW)
B
Y
3
4
C
V
GND
2
5
CC
V
CC
A
C
1
6
Y
B
C in positive logic.
. The I
circuitry disables the outputs,
off
off
TOP-SIDE MARKING
_ _ _CU_
C27_
CU_
Copyright © 2003–2007, Texas Instruments Incorporated
(2)