SN74LVC1G57DSFR

Manufacturer Part NumberSN74LVC1G57DSFR
Description
ManufacturerTexas Instruments, Inc.
SN74LVC1G57DSFR datasheet
 


Specifications of SN74LVC1G57DSFR

Pack_quantity5000Comm_code85423990
Lead_time42EccnEAR99
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CONFIGURABLE MULTIPLE-FUNCTION GATE
FEATURES
1
Available in the Texas Instruments NanoFree™
2
Package
Supports 5-V V
Operation
CC
Inputs Accept Voltages to 5.5 V
Max t
of 6.3 ns at 3.3 V
pd
Low Power Consumption, 10-μA Max I
±24-mA Output Drive at 3.3 V
I
Supports Partial-Power-Down Mode
off
DBV PACKAGE
(TOP VIEW)
In1
In2
1
6
V
GND
2
5
CC
Y
3
4
In0
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
This configurable multiple-function gate is designed for 1.65-V to 5.5-V V
The SN74LVC1G57 features configurable multiple functions. The output state is determined by eight patterns of
3-bit input. The user can choose the logic functions AND, OR, NAND, NOR, XNOR, inverter, and noninverter. All
inputs can be connected to V
or GND.
CC
This device functions as an independent gate, but because of Schmitt action, it may have different input
threshold levels for positive-going (V
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using I
preventing damaging current backflow through the device when it is powered down.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Check for Samples:
SN74LVC1G57
Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
CC
– 1000-V Charged-Device Model (C101)
DCK PACKAGE
(TOP VIEW)
In1
In2
1
6
GND
GND
2
5
V
CC
In0
3
4
Y
DRY PACKAGE
(TOP VIEW)
ln1
1
6
GND
2
5
ln0
3
4
) and negative-going (V
) signals.
T+
T–
SN74LVC1G57
SCES414M – NOVEMBER 2002 – REVISED OCTOBER 2011
DRL PACKAGE
YZP PACKAGE
(TOP VIEW)
(BOTTOM VIEW)
In0
3
4
In1
1
6
In2
GND
2
5
2
5
V
CC
In1
1
6
In0
Y
3
4
DSF PACKAGE
(TOP VIEW)
ln2
ln1
1
6
ln2
GND
V
2
5
CC
V
CC
ln0
Y
3
4
Y
operation.
CC
. The I
circuitry disables the outputs,
off
off
Copyright © 2002–2011, Texas Instruments Incorporated
Y
V
CC
In2