CXA2006 Sony Corporation, CXA2006 Datasheet
CXA2006
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CXA2006 Summary of contents
Page 1
... Digital CCD Camera Head Amplifier Description The CXA2006Q is a bipolar IC developed as a head amplifier for digital CCD cameras. This IC provides the following functions: correlated double sampling, AGC for the CCD signal, GCA for the low- band chroma signal, AMP for high-band chroma and line signals, A/D sample and hold, blanking, A/D reference voltage, and an output driver ...
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... PBRFC MODE SWITCHING AGCCLP SH2 LPF AGC SH3 REF BOTTOM LIN/ AMP VISH GCA – 2 – BLK CAMSH 14 REF 13 TOP 12 OFFSET C CH/ DRV 9 LOUTCLP CXA2006Q AGCCLP CLPOB XRS PBLK OFFSET VRT VRB ...
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... CXA2006Q ( 4.75V) CC Description Camera and video signal selector. 68k Chroma signal and composite video signal selector. 1.35V High-band chroma signal and low-band chroma signal selector. ...
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... SW1 SW2 OFFSET 13.75k 2V 2k 10k 100µA 1.1k 3.75k 4V 3k 20k 100µA 100µA 100µA – 4 – CXA2006Q Description Driver output for A/D 8 converter capable of DRVOUT DC coupling. Dynamic range = 2Vp-p 30k SW1 SW2 Mode CAM 1 0 LIN ...
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... CXA2006Q Description Controls the output offset during camera mode. When 0V: 12 less than (VRB – 200mV) When 3.0V: 10k greater than (VRB + 300mV) Camera signal pre- blanking pulse input. ...
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... AGC clamp capacitor. 16 (Recommended value: 0.1µF) AGC gain control. When 0V: 8dB 38k (Minimum gain) When 3.0V: 38dB (Maximum gain) 20µA 20µA Enables monitoring of the SHD output 19 camera signal. Preset level sample- and-hold pulse input. 127 21 22 10k Data level sample- and-hold pulse input. CXA2006Q ...
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... CXA2006Q Description 66k Clamp pulse used to clamp the dummy 1.45V pixel portion of the input CCD signal. 29k 85µA 14k 2k CCD signal input. 36k 2k 10k LIN mode Common input for 2µ ...
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... CXA2006Q Description 50µA 41k Gain control for the low-band chroma signal (CL). When 0V: 3.5dB (Minimum gain) When 3.0V: 15.5dB 0.86V (Maximum gain) 9k 100µA Low-band chroma signal (CL) input. ...
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... OPEN Min. Typ. Max. Unit and and — 1.9 2.1 2.5 1.9 2.1 2.5 560 660 — –270 –200 3.97 4 4.03 1.9 2 2.1 1.9 2 2.1 –5 8.5 15 8.5 9.5 10.5 8.1 9.1 10.1 16 20.5 — 0.4 CXA2006Q — — 2 ...
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... 0.1µ 20k C6 25p V13 3V GND GND GND SW2 SW3 SW5 SW4 L H OFF OFF POWER SAVE CXA2006Q C7 0.1µ PL4 PL5 PL6 V15 4.7 µ OFF 4.7µ MODE CAM LIN CL CH ...
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... PL1 (CLPDM) PL6 (PBLK) V5 (DIN) Equivalent to CCD signal black level V3 (CH) V4 (PBRFC (LIN) PL2 (SHD) PL3 (SHP) PL5 (XRS) PL7 (VSHP) 1H 2µs 1H 2µs 1H – 11 – CXA2006Q Different for each test Different for each test 1.5V GND 1.5V GND 1.5V GND 2.5V GND ...
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... GND GND GND GND GND – 12 – GND V12 AGCCLP 0.1µ 16 CLPOB 15 BLK XRS 14 PBLK REF 13 TOP OFFSET 12 SW VRT 11 VRB CH/ 4.7µF DRV LOUTCLP A/D IN GND CXA2006Q 4.7µ A/D ...
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... BLK output CAMVISW output DRVOUT output = 4.75V) CC Sig interval OPB interval Signal level Basic black level [ 3] 2.16V – 13 – Idle transfer Sig interval interval 2. 2.7V 2µs Black level 2.16V 2µs 10µs 2.16V [ Approx. 2.65V when OFFSET = 3V Approx. 1.73V when OFFSET = 0V CXA2006Q ...
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... CH/CL DC [CH/CLDC], which gives center potential to the high-band chroma and low-band chroma signals of the video signal. DRV: DRV drives the external A/D. Camera and video (LIN, CH, CL modes) signals are input by switching C/VSW, and offset adjusted signals are output from DRVOUT pin. – 14 – CXA2006Q from 0 to 3V. AGCCONT ...
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... The video signal processing system operates in CL signal mode when PS is high, CAM/VIDEO is low, PB/REC is high and CH/CL is low, or when PS is high, CAM/VIDEO is low, PB/REC is high and CH/CL is high. Video signal processing system timing chart LIN mode LIN/CH input AMP output 9.5dB VISP DRVOUT output – 15 – CXA2006Q and RT 2.4V 2.1V 2.1V ...
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... VISW switches between the LIN, CH and CL low-band chroma signals for the video signal processing system. The signals are switched according to the mode selection. LOUTCLP: LOUTCLP is a clamp circuit which operates when the LIN signal is output to the DRV. The clamp potential is the sync portion, and is 2.1V. – 16 – CXA2006Q ...
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... DC bias so that the center potential of the SIN signal is 2.7V to allow full input. The input level and frequency are respectively 470mVp-p (Max.) and from 1 to 7MHz. CH/CL DC: CH/ bias circuit which operates when the CH signal is output to the DRV. The DC bias potential is 3V. CH mode LIN/CH input AMPOUT output 9.1dB VISH DRVOUT output – 17 – CXA2006Q 2. ...
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... The GCA amplifier controls the gain of the CL signal input to PBRFC. The gain can be varied from 0.4 to 20.5dB by adjusting the RFCONT voltage from 0 to 3V. CH/CL DC: CH/ bias circuit which operates when the CL signal is output to the DRV. The DC bias potential is 3V. CL mode PBREC input GCAOUT output 0.4 to 20.5dB VISH DRVOUT output – 18 – CXA2006Q 2.94V 3V 3V ...
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... CL mode RFGCA gain control supply voltage characteristics V vs. Gain AGCCONT 4. 0.0 1.0 2.0 V [V] AGCCONT V vs. OFFSET OFFSET 700 600 500 400 300 200 100 0 –100 –200 –300 0.0 1.0 2.0 V [V] OFFSET V vs. Gain RFCONT 4. 0.0 1.0 2.0 V [V] RFCONT – 19 – = 5. 4.75V 5.0V CC 3.0 = 5.0V 3.0 CXA2006Q ...
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... V OFFSET CL mode RFGCA gain control temperature characteristics V RFCONT –1 0.0 1.0 V RFCONT – 20 – = 4.75V) CC –20°C 27°C 75° 4.75V CC 2.0 3.0 75°C 27°C –20° 4.75V CC 2.0 3.0 [V] vs. Gain –20°C 27°C 75° 4.75V CC 2.0 3.0 [V] CXA2006Q ...
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... V CC 2.60 2.50 – [°C] CH mode AMP gain temperature characteristics 4.75V 8 60 –20 0 LIN mode AMP gain temperature characteristics 4.75V 8 – – 21 – CXA2006Q Ta vs. Gain (CH mode 4.75V [°C] Ta vs. Gain (CL mode 4.75V [°C] ...
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... CC –75 –80 60 –20 0 – 22 – CXA2006Q 2nd: OUT = 1.8Vp-p 2nd: OUT = 1.4Vp-p 3rd: OUT = 1.8Vp-p 3rd: OUT = 1.4Vp 5MHz [°C] 3rd: OUT = 1.8Vp-p 2nd: OUT = 1.8Vp-p 2nd: OUT = 1.4Vp-p 3rd: OUT = 1.4Vp-p ...
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... SONY CODE EIAJ CODE JEDEC CODE 32PIN QFP (PLASTIC) 9.0 ± 0.2 + 0.3 7.0 – 0 0.15 0.3 – 0.1 0.24 M PACKAGE MATERIAL LEAD TREATMENT QFP-32P-L01 QFP032-P-0707 LEAD MATERIAL PACKAGE MASS – 23 – CXA2006Q 0.1 + 0.35 1.5 – 0.15 + 0.2 0.1 – 0.1 + 0.1 0.127 – 0.05 0° to 10° EPOXY RESIN SOLDER PLATING 42 ALLOY 0.2g ...