CXA2061 Sony Corporation, CXA2061 Datasheet
CXA2061
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CXA2061 Summary of contents
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... Y/C/RGB/D for NTSC Color TVs Description The CXA2061S is a bipolar IC which integrates the luminance signal processing, chroma signal processing, RGB signal processing, and sync and deflection signal processing functions for NTSC system color TVs onto a signal chip. The IC also includes deflection processing functions for wide TVs ...
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... CC – 2 – CXA2061S CC ...
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... G OUT B OUT 24 – 3 – X'tal 46 FSCOUT 45 APC FIL TV/ ABL FIL 41 CVBS2/ GND2 YUV SW 35 SDA 34 SCL YS2/ YS1 CXA2061S ...
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... The threshhold voltage at which ABL begins to have effect can be switched between the bus. CVBS signal/luminance signal input. Input a 1Vp-p (100% white including sync) CVBS signal via a 1µF capacitor. When inputting Y/C separated signal, input the Y signal. CXA2061S ...
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... Input the chroma signal from the comb filter. Standard input level (burst level) is 0.6Vp-p. Capacitor connection for luminance signal clamp. Connect to GND via a 0.1µF capacitor. Input the luminance signal from the comb filter. The signal is input via a 0.1µF capacitor with a level of 2Vp-p. (100% white including sync) CXA2061S ...
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... Description GND (the deflection blocks circuit). V parabola wave output. Internal reference current setting. Connect to GND via a 10kΩ resistor (metal film resistor) with an error less. V sawtooth wave output. The pin 13 and 14 outputs are the reverse polarity of each other. CXA2061S ...
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... At this time, the HD output goes to high impedance, the RGB output are blanked and "1" is output to the 25k status register HNG. To release this status, turn the power off and then on again. – 7 – CXA2061S Description ...
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... The RGB output cutoff can be varied by the bus CUTOFF. The beam current is large during the video interval, so attach a Zener diode of around 4V to this pin to protect the IC and B signal outputs. 2.4Vp-p is outputted during 100% white input. PICTURE: 1Fh DRIVE: 1Fh BRIGHT: 1Fh CXA2061S ...
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... SCP. When setting the bus YUV OUT = 1 and 1.2k connecting 10kΩ resistors to Vcc, Internal YUV signals outputs 60k Power supply – 9 – CXA2061S Description YS1 Vth: 0.7V SLAVE ADDRESS Vth: 7V YS2 Vth Pin: B-Y output 31 Pin: R-Y output 32 Pin: Y output ...
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... YUV SW control. Selects the external YUV input. Vth: 0.7V This switch has a function prohibited forcibly only the external Y input by the register Y SEL. External Y, R-Y and B-Y signal inputs. Input the signal via a 0.01µF capacitor. EY IN: 0.7Vp-p (no sync) ER-Y IN: 0.735Vp-p (75% Color Bar) EB-Y IN: 0.931Vp-p (75% Color Bar) CXA2061S ...
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... CVBS signal input from the TV tuner or chroma signal input. Input a 1Vp-p (including sync) CVBS signal or a chroma signal with a burst level of 300mVp-p via a 1µF capacitor. Power supply (mainly for the chroma block circuit). Chroma APC lag-lead filter connection. Connect CR to GND. CXA2061S ...
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... Pin Symbol No. 46 FSC OUT X'tal Equivalent circuit 200 16k 46 15k 2.5k 47 1.333k – 12 – Description FSC output. Output FSC signal by the register FSC SW. APC crystal connection. X'tal: NTSC crystal (3.579545MHz) CXA2061S ...
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... CXA2061S ...
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... CXA2061S ...
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... CXA2061S ...
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... Be able to select YUV SW 1 BPF ON 0 TRAP ON 3Fh Maximum 0 FSC output OFF 1Fh Center 0 C signal ON 1Fh Center 0 F0 2.5MHz 0 NTSC JAPAN axis 1Fh Center 0 100% 0 1:1 7h Center 7h Center 7h Center 7h Center 1Fh Center 1 PICTURE/BRIGHT mode 0 VTH = 3V 1Fh Center 0 Dynamic color OFF – 16 – CXA2061S ...
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... DC Ievel normal mode 1Fh Center 1Fh Center 1Fh Center 7h Center Fh Compensation amount max Center 7h Center 7h Center 7h Center 7h MAX 3Fh H BLK width control OFF 0 0 OFF 1Fh Center 0 ZOOM OFF 0 Linearity 100% 0 Linearity 100 timing pulse output – 17 – CXA2061S ...
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... B CUTOFF ABL MODE DYNAMIC C GAMMA H SS INTERLACE AFC GAIN V LINEARITY EHT COMP AFC ANGLE RIGHT HBLK HBLK V ZOOM LOWER VLIN CXA2061S Bit0 0 Y SEL C TRAP OFF FSC SW AXIS NTSC PRE/OVER ABL VTH RGB SEL MASK UNDER SCAN 0 1 ...
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... When the status register "KILLER ID OFF" is set up "0", the chroma trap filter is set to OFF (= 1) by microcomputer control Trap filter Trap filter OFF SHP F0 (1): Sharpness f0 selector 0 = 2.5MHz 1 = 3.0MHz SHARPNESS (4): Sharpness gain control 0h = –12dB 7h = +3.5dB Fh = +9dB DC TRAN (1): DC transmission ratio selector 0 = 100 85% PRE/OVER (1): Sharpness preshoot/overshoot ratio control 2:1 – 19 – CXA2061S ...
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... Forced PAL axis mode YUV OUT (1): Switches the R2 IN/G2 IN/B2 IN input pins (Pins 32, 31 and 30 R-Y and B-Y signal output pins IN/G2 IN/B2 IN signal input mode 1 = Pin 30: B-Y output Pin 31: R-Y output Pin 32: Y output (In this case, connect each pin to Vcc via a 10kΩ resistor.) – 20 – CXA2061S ...
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... Fh = 19µA G CUTOFF (4): G output cut-off control (lnput current excluding Ieak amount at the reference pulse 6.5µ 13µ 19µA B CUTOFF (4): B output cut-off control (lnput current excluding Ieak amount at the reference pulse 6.5µ 13µ 19µA – 21 – CXA2061S ...
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... R ON (1): Blanking switch for R output signal without an AKB reference pulse output blanked output (1): Blanking switch for G output signal without an AKB reference pulse output blanked output (1): Blanking switch for B output signal without an AKB reference pulse output blanked output ON – 22 – CXA2061S ...
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... Recommended when shortening the lock time Not used INTERLACE (2): Interlace/non-interlace mode selector Interlace mode 2 = Non-interlace mode (Even fields shifted by +1/2H Non-interlace mode (Odd fields shifted by +1/2H) AFCGAIN (2): AFC loop gain control (H Sync and H VCOPLL High 1 = Medium 2 = Not used 3 = Low – 23 – CXA2061S ...
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... HD W (1): HD pulse width varying switch (Set power-on Normal mode (Pulse width: 25µ Pulse width narrow mode (Use when the FBP rise time from the HD rise is short.) V SIZE (6): Vertical picture size adjustment (VD output gain control –15% (Minimum size) 1Fh = 0% 3Fh = +15% (Maximum size) – 24 – CXA2061S ...
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... TRAPEZIUM (4): Horizontal trapezoidal distortion compensation amount adjustment (Parabola wave phase control 1.5ms advance (Horizontal size for top of picture increases; horizontal size for bottom of picture decreases –1.5ms delay (Horizontal size for top of picture decreases; horizontal size for bottom of picture increases.) – 25 – CXA2061S ...
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... ASPECT = 2Fh. RGB is also blanked during this interval (1): V parabola wave DC Ievel down mode during 4:3 deflection on a 16:9 CRT 0 = OFF (DC Ievel down) In this case, the pin distortion must be readjusted by picture distortion compensation when – 26 – CXA2061S ...
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... Color killer OFF H CENT (1): H VCO status VCO oscillator frequency is higher than the horizontal frequency of the input signal selected by the VIDEO switch VCO oscillator frequency is lower than the horizontal frequency of the input signal selected by the VIDEO switch. – 27 – CXA2061S ...
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... Description of Operation 1. Power-on sequence The CXA2061S does not have an Internal power-on sequence. Therefore, all power-on sequence are controlled 2 by set microcomputer (I C bus controller). 1) Power-on The IC is reset and the RGB outputs are all blanked. H drive starts to oscillate, but oscillation is at the maximum frequency (16kHz or more) and is not synchronized with the input signal in order to prevent FBT (flyback transformer for generating high voltage) H squealing ...
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... Center (Adjust) Center (Adjust) Center (Adjust) Center (Adjust) PictureABL/BrightABL combined mode Vth = 3V Center (Adjust) Dynamic Color OFF YS1 SW normal mode Center (Adjust) Gamma OFF Center (Adjust) Normal Interlace Mode Slice level 1/3 (from Sync Tip) Slice level 1/3 (from Sync Tip) – 29 – CXA2061S ...
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... Various mode setting The CXA2061S contains bus registers for deflection compensation whitch can be set for various wide mode. Wide mode setting registers can be used separately from registers for normal picture distortion adjustment, and once picture distortion adjustment has been performed in fill mode, wide mode setting can be made simply by changing the corresponding register data. • ...
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... In this mode, the H deflection size must be compressed by 25% compared to full mode. The CXA2061S performs compression with a register (EW DC) that compresses the H size. Because excessive current flows to the horizontal deflection circuit in this case, adequate consideration must be given to the allowable power dissipation, etc., of the horizontal deflection coil in the design of the set. In addition, this concern can also be addressed through measures taken external to the IC, such as switching the horizontal deflection coil ...
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... Adjust the following three registers with respect to the 16:9 CRT standard values for the register settings. ASPECT = Adjustment value UPPER VLIN = Adjustment value LOWER VLIN = Adjustment value (7) 4:3 CRT normal mode This is the standard mode for 4:3 CRTs. The register settings are the 4:3 CRT standard values. – 32 – CXA2061S ...
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... ASPECT UP VLIN Wide Zoom LO VLIN (S CORR 4:3 Normal 4:3 CRT standard value ASPECT V compression V UNDER SCAN = 1: V size 80% (compressed to 75% total) – 33 – CXA2061S BUS REGISTER = 0h: V size 75 HBLK width adjustment ON = Adjustment = Adjustment = 1 = 2Fh: V size 100 Zoom ON (V size limited at 75%) ...
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... VIDEO switch The block diagram from the CXA2061S input to the VIDEO switch is as shown in the diagram below. The input is selected and switched by the VIDEO SEL and S SEL settings as shown in the table below. INPUT: 1.0Vp-p TV/C2-IN CVBS1/Y1 IN CVBS2/Y2 IN C1-IN INPUT: 2.0Vp-p COMB-Y IN COMB SEL ...
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... Signal processing The CXA2061S is comprised of sync signal processing, H deflection signal processing, V deflection signal processing, and Y/C/RGB signal processing blocks, all of which are controlled by the I 1) Sync signal processing The Y signal selected by the video switch is sync separated by the horizontal and vertical sync separation circurts ...
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... In addition, the cathode leak current flowing during blanking can be supported up to 100µA. Large currents flowing during the video interval may damage the areas around IK IN sure to connect a Zener diode of about 4V to the IK IN pin bus. An auto cut-off function – 36 – CXA2061S 2 C ...
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... H SYNC SCP (HDW = 0) HD (HDW = 1) RGB BLK 1.2µs (by LEFT HBLK) (H POSI = 1Fh POSI = 3Fh) (H POSI = 0h) 4.6µs 4.3µs 0.275V 6µs 2V 6µs 25µs 19µs 3µs 15.5µs 1.2µs 12µs 2µs 2µs – 37 – VIDEO 3µs 2.9V 1µs 10µs 7.7V 1.2µs 1.2µs (by RIGHT HBLK) CXA2061S ...
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... VTIM 20µ OUT ODD G OUT output B OUT R OUT EVEN G OUT output B OUT 267 268 269 270 271 272 273 – 38 – CXA2061S VIDEO 282 283 VIDEO REF. PULSE 50µs VIDEO REF. PULSE ...
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... Notes on operation Because the RGB signals and deflection signals output from the CXA2061S are DC direct connected, the board pattern must be designed with consideration given to minimizing interference from around the power supply and GND. Do not separate the GND patterns around each pin; a solid earth is ideal. Locate the power supply side of the by-pass capacitor which is inserted between the power supply and GND as near to the pin as possible ...
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... ASPECT 4.2 4 3.8 3.6 3.4 3.2 3 ASPECT = 0 ASPECT = 1F 2.8 ASPECT = 3F 2 Time [ms] 4.5 4 3 4.2 4 3.8 3.6 3.4 3.2 3 2.8 2 4.5 4 3 – 40 – V POSITION V POSITION = 0 V POSITION = 1F V POSITION = Time [ms] V-LINEARITY V-LIN = 0 V-LIN = 7 V-LIN = Time [ms] SCROLL SCROLL = 0 SCROLL = 1F SCROLL = Time [ms] CXA2061S ...
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... CORNER PIN 4.5 4 3.5 3 2.5 CORNER PIN = 0 CORNER PIN = 1F CORNER PIN = Time [ms] 4.2 4 3.8 3.6 3.4 3.2 3 2.8 2 4.2 4 3.8 3.6 3.4 3 – 41 – CXA2061S LO-VLIN LO-VLIN = 0 LO-VLIN = 7 LO-VLIN = Time [ms] PIN TRAPEZIUM PIN TRAPEZIUM = 0 PIN TRAPEZIUM = 7 PIN TRAPEZIUM = Time [ms] ...
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... CXA2061S H POSITION SYNC center t [µs] 18 PIN : DATA SHARPNESS SHARPNESS = 0 SHARPNESS = 7 SHARPNESS = Furequency [MHz] COLOR ...
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... DATA GAMMA 2.5 2 1.5 1 0.5 GAMMA = 3 0 GAMMA = 0 –0 YIN input amplitude [IRE –1 –2 –3 – 100 – 43 – CXA2061S DRIVE DATA ...
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... This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame). 48PIN SDIP (PLASTIC) + 0.4 – 0 1.778 0.5 ± 0.1 0.9 ± 0.15 PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT SDIP-48P-02 SDIP048-P-0600 LEAD MATERIAL PACKAGE WEIGHT – 44 – CXA2061S 0° to 15° EPOXY RESIN SOLDER/PALLADIUM PLATING COPPER / 42 ALLOY 5.1g ...