CXA2112 Sony Corporation, CXA2112 Datasheet
CXA2112
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CXA2112 Summary of contents
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... LCD Driver For the availability of this product, please contact the sales office. Description The CXA2112R is a driver IC developed for use in the 6-input/12-input Sony polysilicon TFT LCD panel (LCX016/017). It has a line invert amplifier and analog de-multiplexers, timing generator and output buffers required for these. CXA2112R can directly drive analog inputs of LCX016/017 ...
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... OFFSET CANCEL – 2 – BIAS VCOM 29 S/H BUFFER 28 27 S/H BUFFER 26 25 S/H BUFFER 24 23 S/H BUFFER 22 S/H BUFFER 21 20 S/H BUFFER CXA2112R GND2 SH_OUT1 NC SH_OUT2 NC SH_OUT3 PV CC D.P D.P PGND NC SH_OUT4 NC SH_OUT5 NC SH_OUT6 ...
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... 150k V DD 50k 145 12 50k – 3 – CXA2112R Description Sample-and-hold position setting. See Tables A-1, A-2 and A-3. Connect as closely as possible to NEXT_IN. Connect as closely as possible to NEXT_OUT. Before/after decision for 12-output. See Table B. 6-output/12-output switch. High: 6-output Low: 12-output. See Table B. ...
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... V CC 145 10k 35 20µ – 4 – CXA2112R Description Scan direction switch. High: forward scan Low: reverse scan Analog GND. Output. VCOM output. Can be set SIGCEN V –2V by Pin 34 input. SIGCEN 500 V : voltage set by Pin 35. ...
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... 100k 50k V DD 10k 44 50k – 5 – CXA2112R Description Vcc circuit bias current setting. Normally, connect 27kΩ (±1%) between this pin and GND. SID signal waveform output. Connect to an external buffer for panel. Power GND. Power Vcc. Connect directly to Vcc. ...
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... 50µ – 6 – CXA2112R Description Sample-and-hold circuit common input. Should not be less than 2V. Invert amplifier output. Invert amplifier input. Video signal input offset setting. Inputs 100% white level. Dot clock phase adjustment. 15V power supply. ...
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... 150k V DD 50k 145 62 50k – 7 – CXA2112R Description Dot clock input. Dot clock phase invert control. Phase adjusted dot clock output. On-chip timing generator clock input. Connect directly to Pins 54 and 55. Horizontal sync signal PRG input. Refer to Timing Chart. ...
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... Standard Symbol I/O No. voltage level DGND 8, 9, 24, 25, D.P GND 40, 41, 56 11, 14, 15, 16, 18, 20, 22, NC 28, 30, 36, 60, 63, 64 Equivalent circuit 5V – 8 – CXA2112R Description 5V power supply. Digital GND. Die pad. Used as thermal radiator on board. Connect to GND. No connection. Not connected to anything. ...
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... SID_IN — 30 — is 2.5V/11.5V. Vsig – 2 — Vsig or less — 700 — — 150 — so that IN — output CLK 100 115 output CLK 13.5 2 2.5 CXA2112R mA mA times V/µs MHz ns times V/µs V V/µs V/µs mVp-p MHz MHz V V ...
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... Minimum VOUT1 to VOUT6 value subtracted from maximum VOUT1 to VOUT6 value. Unless otherwise specified, pin setting conditions are as follows. (48) OFFSET = 3.3V, (47) VIDEO_IN = 2.0V, (42) SID_OFST = 3.3V, (39) SID_IN = 2.3V, (35) SIGCEN = 7.0V, (34) VCOMOFST = 0.0V, (1) POS_CNT1 = 0.0V, (2) POS_CNT2 = 0.0V, (5) F/R_CNT = 5.0V, (10) S/12_CNT = 5.0V, (13) DIR_CNT = 5.0V, (49) DLY_CNT = 4.0V, (52) INV_CNT = 5.0V, (44) FRP = 0.0V 65MHz CLK – 10 – CXA2112R ...
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... D.P 25 S/H BUFFER D.P 24 PGND 23 S/H BUFFER NC 22 SH_OUT4 S/H BUFFER SH_OUT5 S/H BUFFER SH_OUT6 SW3 V CC 15.5V CXA2112R SID V 1 OUT C1 270pF V 2 OUT C2 270pF V 3 OUT C3 270pF OUT C4 270pF V 5 OUT C5 270pF V 6 OUT C6 270pF ...
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... Invert operation is carried out with SIGCEN (Pin 35) potential as center voltage of signal inversion. OFFSET (Pin 48) input voltage corresponds to 100% white level of the signal input to VIDEO_IN. When used in combination with the CXA2111R, connect the CXA2111R V33 (Pin 8) output to the CXA2112R OFFSET. When use DA converter output as the VIDEO signal, connect DA converter maximum output voltage (normally, DA converter's supply voltage) ...
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... SIGCEN voltage. When VCOMOFST (Pin 34) is changed from 0 to 10V, VCOMOUT changes from (SIGCEN potential) to (SIGCEN potential) – 2V. V SID_IN Output level when input SID_OFST level approx SID_IN approx. 1V approx. 1V – 13 – CXA2112R SID_OFST level SIGCEN potential ...
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... Depending on the operation mode setting, scan direction (SH_OUT1 SH_OUT1), number of outputs (6-output/12-output) and sample-and-hold position (output phase) can be changed – 14 – SH_OUT6 and SH_OUT6 CXA2112R ...
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... Operation Mode Setting 1) For each RGB channel, LCX016 requires demultiplexed 6 analog outputs (one CXA2112R), and LCX017 needs 12 (two CXA2112R). In either case, scan direction switching, sample-and-hold position and phase can be controlled. The mode input pin settings for each case are shown below. ...
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... H H Table A-2 R1 sets the level for setting values 1 and 2. The appropriate resistance value changes depending on numbers of CXA2112R are driven by one CMOS logic (1-channel or RGB 3-channel drive, or one CXA2112R (6- outputs/ch) or two CXA2112R (12-outputs/ch)). Recommended resistance values are given in Table A-3. CMOS Logic Connection ...
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... Dot Clock Phase Adjustment The CXA2112R has phase adjustment function for input dot clock to achieve high precision and stable operation. High definition images with no jitter and flicker can be reproduced by this adjustment. De-multiplexer operation timing is generated from the clock input to CLK_IN (Pin 59) and CLK_IN/ (Pin 61) (ECL differential) ...
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... Input Video Signal • Please be sure that the video signal amplitude (0% black level to 100% white level) which inputs to sample and hold (SH_IN (Pin 45)) does not exceed 3.5V Also, as for inputting to sample and hold, do not apply DC level lower during operation. PP. – 18 – CXA2112R ...
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... BIAS VCOM SH_OUT2 29 S/H BUFFER NC 28 SH_OUT3 27 S/H BUFFER D.P 25 S/H BUFFER D.P 0.1µ 10µ 24 PGND 23 S/H BUFFER NC 22 SH_OUT4 S/H BUFFER SH_OUT5 S/H BUFFER SH_OUT6 15.5V CXA2112R 3.3 3 PSIG 24 COM 7 SIG1 5 SIG2 LCX016 LCD panel 3 SIG3 2 SIG4 4 SIG5 6 SIG6 ...
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... OFFSET CANCEL S/H S/H BUFFER SH_OUT3 27 OFFSET CANCEL NC 28 S/H S/H BUFFER SH_OUT2 29 NC BIAS VCOM 30 SH_OUT1 31 GND2 27k 15.5V 5V CXA2112R 1 PSIG 31 COM 3 VSIG1 4 VSIG2 5 VSIG3 6 VSIG4 7 VSIG5 8 VSIG6 LCX017 14 VSIG12 13 VSIG11 12 VSIG10 11 VSIG9 10 VSIG8 9 VSIG7 ...
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... INV_CNT = Low INV_CNT = High INV_CNT = Low 3 3.5 4 4.5 DLY_CNT (Pin 49) voltage [V] SID_IN = 4.000V FRP = High FRP = Low SID_OFST (Pin 42) voltage [V] SID_OFST = 5.000V FRP = High FRP = Low SID_IN (Pin 39) voltage [V] CXA2112R ...
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... INV_OUT voltage vs. OFFSET voltage (2) 14 VIDEO_IN = 3.500V OFFSET (Pin48) voltage [V] INV_OUT voltage vs. VIDEO_IN voltage (2) 14 OFFSET =5.000V VIDEO_IN (Pin 47) voltage [ – 22 – CXA2112R FRP = High FRP = Low FRP = High FRP = Low ...
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... This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame). 64PIN LQFP (PLASTIC) 16.0 ± 0.2 14.0 ± 0 0.08 0.37 – 0.07 0.13 M 0.25 0.1 ± 0.1 0° to 10° DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT LQFP-64P-L02 LQFP064-P-1414 LEAD MATERIAL PACKAGE MASS – 23 – 1.7MAX 0 0.08 0.37 – 0.07 (0.35) DETAIL B EPOXY RESIN PALLADIUM PLATING COPPER ALLOY 0.7g CXA2112R ...