M66307SP Mitsubishi, M66307SP Datasheet

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M66307SP

Manufacturer Part Number
M66307SP
Description
LINE SCAN BUFFER with 16-BIT MPU BUS COMPATIBLE INPUTS
Manufacturer
Mitsubishi
Datasheet
DESCRIPTION
The M66307SP/FP is an integrated circuit consisting of a line buffer
with static memory, manufactured by the silicon gate CMOS pro-
cess, which satisfies A3-paper 400DPI requirements. It converts the
stored data from the 16-bit MPU bus into serial data and outputs it at
a transfer rate of up to 10Mbps synchronously with the external data
request clock or an arbitrary continuous clock.
FEATURES
(1) Synchronized with an arbitrary continuous clock ( IN) on the
(2) Synchronized with the data request clock (CLK IN) on the pe-
(1) Toggle configuration
(2) 32-bit bus configuration
BLOCK DIAGRAM
16-bit MPU bus compatible
Writing data via DMAC is possible
320-word (5,120-bit) static RAM
Data output rate of up to 10Mbps
Built-in function to add fixed data of a specified length at the be-
ginning of output data (Fixed data: Continuous High bit or Low bit
data)
The output format can be selected between FIFO or LIFO.
The output method can be selected from two:
Up to two devices can be cascaded.
High fan-out outputs (CLK/ OUT, DATA OUT).
Io= 24mA
( 4mA for INTR and DREQ
8mA for BUSY/ORDY)
CLK/
system side; the frequency of clock output (CLK/ OUT) can
be divided by 1, 2, 4, 8, or 16.
ripheral equipment side.
RESET
DACK
CLKE
TOG
EXD
C/D
WR
D
D
D
D
D
D
CS
D
D
D
D
D
D
D
D
D
D
IN
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
10
11
23
24
25
26
27
28
29
30
31
20
21
14
15
12
9
1
2
3
4
5
6
7
8
16
control
circuit
Write
16
16
Expansion
Command registers
DREQ words register
control
control
control
Reset
circuit
Clock
circuit
circuit
Mode register
length register
Fixed data
Frequency
divider
LINE SCAN BUFFER with 16-BIT MPU BUS COMPATIBLE INPUTS
LINE SCAN BUFFER with 16BIT MPU BUS COMPATIBLE INPUTS
16
Write/send
address
control
circuit
APPLICATION
Image-handling general OA equipment
320 word
Clock signal
select circuit
PIN CONFIGURATION (TOP VIEW)
INTERRUPT REQUEST
CMOS
SRAM
The clock input (CLK/ IN) contains a Schmitt trigger.
The reset (RESET), Write (WR) and toggle input (TOG) contain
negative noise reduction circuits.
CLOCK INPUT
CHIP SELECT INPUT
RESET INPUT
CLOCK ENABLE
COMMAND/DATA
CONTROL INPUT
DATA INPUTS
WRITE CONTROL
OUTPUT
13
INPUT
GND V
INPUT
9
16
16
CLK/
(0V)GND
RESET
CLKE
INTR
32
CC
C/D
D
D
D
D
D
D
WR
CS
4
D
D
M66307SP/FP
IN
10
11
12
13
14
15
9
8
Outline 32P4B
13
9
MITSUBISHI DIGITAL ASSP
16
10
11
12
13
14
15
1
2
3
4
5
6
7
8
9
MITSUBISHI DIGITAL ASSP
Output
control
Output
control
Output
control
Output
control
circuit
circuit
circuit
circuit
32P2W-A
M66307SP/FP
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
D
D
D
D
D
D
D
D
DACK
DREQ
EXD
TOG
CLK/
DATA OUT
BUSY/ORDY
22
13
17
18
19
CC
7
6
5
4
3
2
1
0
(5V)
DREQ
INTR
BUSY/ORDY
DATA OUT
CLK/
DATA INPUTS
EXTENDED D INPUT
TOGGLE INPUT
DMA ACKNOWLEDGE
OUT
DMA REQUEST
DATA OUTPUT
OUTPUT
CLOCK
OUTPUT
OUT
INPUT
BUSY/
OUTPUT
READY
OUTPUT
1

Related parts for M66307SP

M66307SP Summary of contents

Page 1

... DESCRIPTION The M66307SP/ integrated circuit consisting of a line buffer with static memory, manufactured by the silicon gate CMOS pro- cess, which satisfies A3-paper 400DPI requirements. It converts the stored data from the 16-bit MPU bus into serial data and outputs transfer rate 10Mbps synchronously with the external data request clock or an arbitrary continuous clock ...

Page 2

... WR RESET IN DACK DREQ INTR BUSY DATA CLK/ CLKE CLK IN OUT OUT ORDY IN (indicated by broken line MITSUBISHI DIGITAL ASSP M66307SP/FP Address bus Control bus System bus interface section Data bus Peripheral equipment interface section ...

Page 3

... LSB/MSB and LIFO/FIFO. While the data is output, the M66307 outputs the Busy/Output Ready signal (BUSY/ORDY). When one line length of data is output, BUSY/ORDY is cleared and an interrupt request signal (INTR) is output. M66307SP/FP 3 ...

Page 4

... YES Set to send mode (BUSY/ORDY output) Outputting data C/D=1 Outputting data Set for transmit for one line length repeat request completed? (INTR output) YES YES Repetitive output NO Completed? MITSUBISHI DIGITAL ASSP M66307SP/FP Static mode Set for operation C/D=1 stop Write mode Send mode ...

Page 5

... LINE SCAN BUFFER with 16-BIT MPU BUS COMPATIBLE INPUTS Function . CC IN, CLKE is invalid so that this pin must be pulled- can be divided into one of five smaller frequencies when the peripheral CC MITSUBISHI DIGITAL ASSP M66307SP/FP or pulled-down to GND generally used as . (See the CC or pull down it to GND. 5 ...

Page 6

... There are eight kinds of commands classified by the upper four bit (D15 to D12). Function The M66307 cannot be accessed. Command is stored in the internal command register. (During MPU cycle) Data is stored in the internal memory. (During DMA cycle) MITSUBISHI DIGITAL ASSP M66307SP/FP ...

Page 7

... One line fixed data setting command 7 Transmit repeat request command Group 4 8 Stop command Command Group 1 Group 2 Group 3 Group 4 Mode Static Write Send complete (BUSY=“H”) Send Send (BUSY=“L”) Note : Command store is valid within Fig. 3 Command store Map Contents M66307SP/ ...

Page 8

... Second word use 1 First word Toggle Mode inversion Second word MITSUBISHI DIGITAL ASSP M66307SP/FP (1= IN, 0=CLK IN) CLK FLAG Toggle extension flag(1=toggle; 0=normal use) DREQ mode flag(1=DREQ mode; 0=not DREQ mode) Fixed beginning data output flag (1=output; 0=not output) Fixed data polarity flag (1=High; 0=Low) ...

Page 9

... LINE SCAN BUFFER with 16-BIT MPU BUS COMPATIBLE INPUTS Output format Write mode set 1WORD set Fixed data Static mode Fixed beginning Output format data length (n) set set Write mode set MITSUBISHI DIGITAL ASSP M66307SP/FP ( N-1 ) WORD NWORD Write mode 1WORD (N-1)WORD NWORD Fixed data Write mode DMA cycle 9 ...

Page 10

... LIFO IN FIFO With fixed beginning data output LIFO 16–2 N 16– 16+1 DN3 DN2 DN1 DN0 MITSUBISHI DIGITAL ASSP M66307SP/FP MSB Fig. 8 LSB Fig. 11 MSB LSB MSB Fig. 9 LSB MSB LSB MSB Fig. 10 LSB MSB LSB ...

Page 11

... DO1 DO2 DNC DND DNF DNE DND D03 D02 DN0 DN1 DN2 DOC DOD DOE MITSUBISHI DIGITAL ASSP M66307SP/FP Write mode set Note : Y=(n+1 (Note) ( Fixed data ) DN0 Fixed data Write mode set DN0 Fixed data Write mode set (Note) ( Fixed data ...

Page 12

... I =+8mA OL I =–4mA OH DREQ, INT I =+4mA Output pin open Output pin open MITSUBISHI DIGITAL ASSP M66307SP/FP Rating –0.3~+7.0 –0.3~V +0.3 CC 0~V CC 700 –65~+150 Unit Max Limits Typ. Max. ...

Page 13

... LINE SCAN BUFFER with 16-BIT MPU BUS COMPATIBLE INPUTS =5V 10%, GND=0V unless otherwise noted) CC Test condition ) or fall time (t ) may cause erroneous operation MITSUBISHI DIGITAL ASSP M66307SP/FP Limits Unit Min. Typ. Max. 100 ...

Page 14

... L C =50pF L C =50pF L C =50pF L C =50pF L C =150pF L C =50pF L C =50pF L C =50pF L 0~3V 6ns 6ns 1.3V MITSUBISHI DIGITAL ASSP M66307SP/FP Limits Unit Min. Typ. Max 100 100 100 100 ...

Page 15

... N is set. When the DREQ mode flag is not set, DREQ is tied High. LINE SCAN BUFFER with 16-BIT MPU BUS COMPATIBLE INPUTS su(A-W) h(W- su(A-W) h(W- su(D-W) h(W- su(DAC-W) h(W-DAC su(D-W) h(W-D) t rec(W) Number of transfer words PHL(W-DRE) Fixed data PHL(W-DO) PLH(W-DO) MITSUBISHI DIGITAL ASSP M66307SP/FP N+1 t PLH(W-DRE) 15 ...

Page 16

... – PHL Fixed data t ,t PLH PHL( I-DO) t PHL(W-BUS) MITSUBISHI DIGITAL ASSP M66307SP/FP Write mode t rec(CI-W) Fixed data t PLH(W-INT) Write mode t t rec(CI-W) h(CI-CE) Fixed data Write mode t PLH Fixed data t PLH( I-BUS PHL( I-INT) ...

Page 17

... Send mode setting TOG WR CLK IN BUSY/ORDY TOG CLKE CLK IN LINE SCAN BUFFER with 16-BIT MPU BUS COMPATIBLE INPUTS t W( PLH(T-DO) PHL(T-DO) Fixed data t PLH(T-INT) t W(T) t rec(W-T) t rec(T-CI) t W(T) t rec(T-CI) t rec(CI-T) t h(CI-CE) MITSUBISHI DIGITAL ASSP M66307SP/FP t rec(R-W) t rec(T-W) t PHL(T-DRE) t PHL(T-BUS) t su(CE-CI) 17 ...

Page 18

... C/D WR DACK DREQ INTR (2) Connection example for DMA transfer Image memory and memory management unit C/D WR DACK DREQ INTR 18 LINE SCAN BUFFER with 16-BIT MPU BUS COMPATIBLE INPUTS V CC N.C. MITSUBISHI DIGITAL ASSP M66307SP/FP MPU INT R/W MPU R/W DMAC DACK DREQ R/W ...

Page 19

... DACK C/D DREQ C/D RES EXD RES INTR TOG INTR CLKE DO CLKE B/O GND GND MITSUBISHI DIGITAL ASSP M66307SP/ DACK DREQ EXD TOG C/ O CLK/ OUT DO DATA OUT B/O CLKE CLK IN ORDY TOG 74, one chip 2/2 ...

Page 20

... Toggle operation is feasible when the circuit is connected as shown in Fig. 12 When IN is used: (i) Toggle operation is feasible when the circuit is connected as shown in Fig. 13. (ii) At the initial setting, set clock input to CLK IN. IN cannot be selected. (iii) Divider clock output is not feasible. M66307SP/FP Slave IC ...

Page 21

... DACK CS C/D DREQ C RES EXD RES INTR TOG INTR CLKE DO CLKE B/O GND GND MITSUBISHI DIGITAL ASSP M66307SP/ DACK DREQ V CC EXD TOG C/ O CLK/ OUT DO DATA OUT B/O CLKE CLK IN ORDY 74, one chip ...

Page 22

... Output format MSB D31(1)~D0(1), D31(2)~D0(2), D31(3)~D0(3) FIFO LSB D0(1)~D31(1), D0(2)~D31(2), D0(3)~D31(3) MSB D31(3)~D0(3), D31(2)~D0(2), D31(1)~D0(1) LIFO LSB D0(3)~D31(3), D0(2)~D31(2), D0(1)~D31(1) D0(n) and D31(n): 32-bit parallel data stored at the n-th position. M66307SP/FP Slave IC Static mode Write mode Send mode Write mode Serial output data ...

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