CXA3026 Sony Corporation, CXA3026 Datasheet
CXA3026
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CXA3026 Summary of contents
Page 1
... Flash A/D Converter Description The CXA3026AQ is an 8-bit high-speed flash A/D converter capable of digitizing analog signals at the maximum rate of 140MSPS. ECL, PECL or TTL can be selected as the digital input level in accordance with the application. The TTL digital output level allows 1: 2 demultiplexed output. ...
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... DGND3 – 1.05 DGND3 – 0.5 V DGND3 – 3.2 DGND3 – 1.4 V DGND3 – 0.5 DGND3 – 1.4 2.0 0 DGND1 0.4 0.8 100 140 +75 –20 DGND3 V (max DGND3–1.2V (min.) IL CXA3026AQ Max. +5.25 V +0.05 V +0.05 V –4. +4.1 V +2 MSPS MSPS +75 °C ...
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... Select Q 45 SELECT DGND1 —3— DGND3 (MSB) P1D7 40 P1D6 39 P1D5 38 P1D4 37 P1D3 36 P1D2 35 P1D1 34 33 P1D0 (LSB) (MSB) P2D7 28 P2D6 27 P2D5 26 P2D4 25 P2D3 24 P2D2 23 P2D1 22 P2D0 21 (LSB CLKOUT DGND2 CXA3026AQ ...
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... —4— CXA3026AQ Description Analog ground. Separated from the digital ground. Analog power supply. Separated from the digital power supply. Digital ground. Digital power supply. Digital power supply. Ground for ECL input for PECL and TTL input. ...
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... DGND1 —5— CXA3026AQ Description Clock input. Reset input. When left open, this input goes to high level. When the input is set to low level, the built-in CLK frequency divider circuit can be reset. Data output polarity inversion input. When left open, this input goes to high level ...
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... Reference voltage mid point. By-pass to AGND with a 0.1 µF chip capacitor. Bottom reference voltage. By-pass to AGND with a 1 µF tantal capacitor and a 0.1 µF chip capacitor. Analog input. Vref Port 1 side data output. Port 2 side data output Clock output. (See Table 2. Operating Mode Table.) CXA3026AQ ...
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... DGND3 – 1.2 –50 +50 – 2.0 0.8 1.5 –50 0 –500 0 5 2.4 0.5 140 10 3 4.5 6 3.0 3.0 3 CXA3026AQ Unit bits LSB LSB pF kΩ µA Ω µA µ µA µ MSPS ...
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... RB INV —8— CXA3026AQ Min. Typ. Max. Unit 150 MHz –12 10 TPS – ...
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... Where (LSB) is the deviation of the output codes when the largest slew rate point is sampled at the clock which has exactly the same frequency as the analog input signal, the aperture jitter Taj is: ∆ 256 2 πf Taj = / = / ( ) ∆ Comparator Pulse B A>B Counter CXA3026AQ 8 Logic Analizer 1024 samples (LSB) ...
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... Description of Operating Modes The CXA3026AQ has two types of operating modes which are selected with Pin 45 (SELECT). Operating Maximum SELECT mode conversion rate DMUX mode V 140MSPS CC Straight mode GND 100MSPS 1. DMUX mode (See Application Circuit 1– (1), (2) and (3).) Set the SELECT pin to V for this mode ...
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... The A/D converter can operate at Fc (min.) = 100MSPS in this mode. Digital input level and supply voltage settings The logic input level for the CXA3026AQ supports ECL, PECL and TTL levels. The power supplies (DV 3, DGND3) for the logic input block must be set to match the logic input (CLK and EE RESET signals) level ...
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... P2D0 to P2D7 8-bit Digital Data +5V(D) —12— CXA3026AQ 8-bit Digital Data Latch 8-bit Digital Data Latch 8-bit Digital Data Latch 8-bit Digital Data Latch 8-bit Digital Data Latch 8-bit Digital Data Latch ...
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... P1D0 to P1D7 36 8-bit Digital Data +5V(D) —13— CXA3026AQ 8-bit Digital Data Latch 8-bit Digital Data Latch 8-bit Digital Data Latch ...
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... Short the analog system and digital system at one point immediately under the A/D converter. See the Notes on Operation. is the chip capacitor of 0.1µF. —14— Analog input 2V 1µ RESETN/E RESET/E 47 RESETN/T 46 SELECT 45 INV 44 CLKOUT DGND2 41 P1D7 40 P1D6 39 P1D5 38 P1D4 CXA3026AQ ...
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... Tds 4.5ns (typ Tpw1 Tpw0 Tdo2;8ns (typ.) 6.5ns (min.) 10ns (max.) 2.0V N–4 N–3 N–2 0.8V 2.0V N–5 N–4 N–3 0.8V Td_clk;7ns (typ.) 4.5ns (min.) 8ns (max.) 2.0V 0.8V —15— N+6 N+5 N+4 Tdo2;8ns (typ.) 6.5ns (min.) 10ns (max.) 2.0V N+1 N+3 0.8V 2.0V N N+2 0.8V T Tdo1 T+1ns (typ.) 2.0V 2.0V 0.8V 0.8V N+2 N+3 N+1 N–1 N N–2 N–1 CXA3026AQ N+7 T ...
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... P1D/out Latch 8bit P2D/out CLKOUT 8bit P1D/out 8bit P2D/out CLKOUT 8bit P1D/out 8bit P2D/out CLKOUT 7ns Td-clk (min) 5.0ns (4.5ns) Td-clk (max) 7.5ns (8.0ns) Tdo2 (min) 7.0ns (6.5ns) Tdo2 (max) 9.5ns (10ns) —16— CXA3026AQ ts (min) th (min) 2.5ns 6.5ns 14ns ...
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... Notes on Operation • The CXA3026AQ is a high-speed A/D converter which is capable of TTL, ECL and PECL level clock input. Characteristic impedance should be properly matched to ensure optimum performance during high-speed operation. • The power supply and grounding have a profound influence on converter performance. The power supply and grounding method are particularly important during high-speed operation ...
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... Analog input voltage [V] Current consumption vs. Conversion rate characteristics response 170 160 150 140 130 – Conversion rate [MSPS] Reference current vs. Ambient temperature characteristics –25 Ta—Ambient temperature [°C] —18— CXA3026AQ f CLK fin= –1kHz 4 DMUX mode C 5pF L= 70 140 25 75 ...
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... Error>16LSB –9 Error rate: 10 160 150 140 –25 25 Ta—Ambient temperature [°C] Error rate vs. Conversion rate characteristics 10 – CLK fin= 10 – 7 Error>16LSB 10 – – 9 – 140 Fc–Conversion rate [MSPS] TPS 75 —19— CXA3026AQ –1kHz 4 160 180 ...
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... Description The CXA3026AQ Evaluation Board is a special board designed to maximize and facilitate the evaluation performance of the CXA3026AQ. After latching the CXA3026AQ output data with a frequency divided clock, the analog signal can be regenerated by a 10-bit high-speed D/A converter. The latched data can also be extracted externally via a 24-pin cable connector ...
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... CXA3026AQ ...
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... DIR.IN 7. S2: Setting junction for the clock frequency division ratio. The operating speed after latching is determined by the frequency division ratio set here. When set to CLK OUT, it operates according to the CXA3026AQ clock output. 8. SW1 SELECT: CXA3026AQ output mode selector switch. 9. SW2 A/D INV: CXA3026AQ output polarity inversion switch ...
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... In the evaluation board of the CXA3026AQ,CLC404 (Comlinear) is employed for IC2 to drive the analog input signal. Though,CLC505 (Comlinear) can also be used instead of CLC404, there should be a little change in the peripheral circuit in this case. ...
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... CON7 P1 side DATA (TTL) CLK CON7 P1 side DATA N–6 (TTL) DATA N–6 CON4 P1 side OUT (Analog regeneration waveform) Operating Conditions CXA3026AQ operating mode Anaiong S2 setting N+1 2Vp N–3 Approximately 9.0ns 0 to –1V : Straight mode : DIR IN pin input : 1/2 frequency divided clock —24— ...
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... DGND 14 R27 130 DGND R25 R26 130 130 CLK 10H136 (PECL CXA3026AQ INV CLKOUT P1D7 P1D6 P1D5 P1D4 P1D3 P1D2 P1D1 P1D0 P1D3 36 P1D2 35 P1D1 34 P1D0 33 C33 0.1µF DGND2 DGND ...
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... NC DGND 12 17 C56 CLKN INV 13 16 0.1µF CLK C50 0.1µF R41 620 DV EE CON8 P2 side DATA CXA3026AQ AGND R42 R43 R4 1k 270 2k D2 TL431CP C13 1µ CON4 AGND P1 side OUT AGND DGND DV EE AGND R44 R45 R5 1k ...
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... R13, 23 33, 37, 38 R14 27 36, 39, 40 FRD-25SR (0.25W) 130Ω R15, 16, 43, 45 R17 R20, 22, 42, 44 R21 R41 Component side silk diagram —27— CXA3026AQ Product name Function RJ-5W-1K 1kΩ volume resistor RJ-5W-2K 2kΩ volume resistor RJ-5W-10K 10kΩ volume resistor RGLD4X621J 620Ω ...
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... Component side pattern diagram Solder side pattern diagram —28— CXA3026AQ ...
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... This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame). 48PIN QFP (PLASTIC) 15.3 ± 0.4 + 0.4 12.0 – 0 0.15 0.3 – 0.1 M ± 0.12 PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT QFP-48P-L04 LEAD MATERIAL QFP048-P-1212-B PACKAGE WEIGHT —29— + 0.1 0.15 – 0.05 0.15 + 0.2 0.1 – 0.1 + 0.35 2.2 – 0.15 EPOXY RESIN SOLDER / PALLADIUM PLATING COPPER / 42 ALLOY 0.7g CXA3026AQ ...