CXA3197 Sony Corporation, CXA3197 Datasheet
CXA3197
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CXA3197 Summary of contents
Page 1
... D/A Converter Description The CXA3197R is a high-speed D/A converter which can perform multiplexed input of two system 10-bit data. This IC realizes a maximum conversion rate 125MSPS. Multiplexed operation is possible by inputing the 1/2 frequency-divided clock or by halving the frequency of the clock internally with the clock frequency divider circuit having the reset pin ...
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... Min. Typ. Max. AGND2 + 1.03 V DGND1 + 0.8 1 – 1. – 3 0.5 0.8 DV 3.5 3.5 125 100 ≥ 10k 50 50 1.5 2.0 0.75 1.0 – (Max (Min.) IL DGND1 CXA3197R Unit – 0 – 1 MSPS MSPS Ω 2.1 V 1.05 V +75 °C ...
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... AV O – AGND2 + 1.25V AGND2 + 0.65V to AGND2 + 1.03V 5V 0V Clamp voltage TTL TTL TTL 5V — 0V – 3 – CXA3197R [ ] Typical voltage level for dual power supply TTL TTL TTL TTL TTL PECL PECL TTL PECL PECL –5V TTL TTL TTL 0V 0V (typ ...
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... RESETN POLARITY 39 44 DGND1 VOCLP INV 10bit A 10bit MUX 10bit DGND2 – 4 – 10bit Latch AGND2 Current Cont. BGR CXA3197R AOUTP 32 31 AOUTN 34 VREF 35 VSET 33 AGND2 37 ...
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... DGND1 TTL TTL 17 DGND1 TTL TTL 19 DGND1 – 5 – CXA3197R Description Side A data input. 1.5V Side B data input. 1/2 frequency-divided clock input. Use this pin in MUX.1A or MUX.2 mode. Leave open for other 1.5V modes 1/2 frequency-divided clock output. The 1/2 frequency- divided clock signal ...
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... At this time, leave Pin 19 open. CLKP/E and CLKN/E are complementary and should be used together. CLKP/E complementary input. Reset signal input. When multiple CXA3197R are operated at the same time in MUX.1A or MUX.1B mode, the start timing of the internal 1/2 frequency divider circuits should be 1.5V matched. ...
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... FS O – BGR (Typ AGND2 – 7 – CXA3197R Description Digital power supply. Analog output power supply. The AV O pin voltage CC can be varied within the range that satisfies the analog output compliance voltage. Negative analog output. The inverse of the ...
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... TTL 40 DGND1 TTL DGND1 5V 0V – 8 – CXA3197R Description Analog power supply. TTL output High level clamp. A TTL level signal output from the DIV2OUT pin in MUX.1A mode. The TTL High level voltage can be clamped to the 38 value approximately equivalent to the voltage applied to this pin ...
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... CXA3197R Unit bit LSB LSB LSB V V µA µ µA µ µA µ µA µA µA µ Ω F.S. ppm/°C ...
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... O – VOF) – – 10 – Typ. Max. AGND2 + 1.25 AGND2 + 1.32 AGND2 + 1.32 AGND2 + 1.25 250 0 96 129 0.432 1.5 0.38 0.001 0.2 0.05 0.3 0.001 2 (LSB) (LSB that it satisfies the CC CXA3197R Unit V V ppm/°C µA MHz ...
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... AV CC consumption in power saving mode. VREF pin voltage External resistance 2 pin to the VREF pin. This value must be added to obtain the actual current = I REFOUT BGR VREF 34 In power saving mode: I REFOUT AGND2 – 11 – VREF pin voltage = External resistance CXA3197R ...
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... MUX.1A characteristics Switching – 12 – CXA3197R mode MUX.1B ...
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... MUX.2 characteristics Switching – 13 – modes SELE.B SELE.A, CXA3197R ...
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... DA0 AOUTP DA9 DB0 10 to DB9 AOUTN CXA3197R CLK/T +5 VSET DGND2 INV AGND2 –5V +5 – 14 – CXA3197R DVM 50 (Digital Voltmeter) 50 937.5mV PC – ...
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... VSET DGND2 AGND2 +5V –5V 1 DGND1 AOUTP AOUTN 50 CXA3197R VREF 1mA 0.1µF VSET DGND2 AGND2 –5V –5V – 15 – Oscilloscope 50 50 –5V Oscilloscope AOUTP output 100mVp-p VSET pin 50 output CXA3197R 0V) AGND2 + 937.5mV ...
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... Data input code D0 (LSB) Analog output level AOUTP AOUTN AV O – – CXA3197R O – – ...
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... The CXA3197R can input data divided into two systems: A (DA0 to DA9) and B (DB0 to DB9), internally multiplex the data, and output analog signal, making it possible to halve the data rate. This lets the CXA3197R support the TTL data input level in contrast to the ECL data input level for conventional high-speed D/A converters ...
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... When using the multiple CXA3197R in MUX.1A mode, the start timing of the 1/2 frequency-divided clocks becomes out of phase, producing operation such as that shown in the example below countermeasure, the MUX.1A mode has a function that matches the start timing of the 1/2 frequency-divided clocks with the reset signal ...
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... After the reset is released, the internal 1/2 frequency-divided signal commences at the first clock edge sure to input the data in a manner that satisfies the setup time (ts) and hold time (th) with respect to this clock edge. – 19 – CXA3197R CXA3197R (MUX.1B mode) Clock input pin 1/2 Reset input pin DA0 to DA9 ...
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... Like MUX.1A mode, when using the multiple CXA3197R in MUX.1B mode, the start timing of the 1/2 frequency-divided clocks becomes out of phase, producing operation such as that shown in the example below countermeasure, the MUX.1B mode also has a function that matches the start timing of the 1/2 frequency-divided clocks with the reset signal ...
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... DIV2IN signal. See the timing chart for the detailed timing. Clock DIV2IN signal A0 System A data B0 System B data Analog output signal ts_DIV th_DIV – 21 – CXA3197R CXA3197R (MUX.2 mode) Clock input pin DIV2IN input pin DA0 to DA9 DB0 to DB9 ...
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... PD 0 Clock C2 signal ts th System A data A0 A1 System B data Analog output signal ts_C2 th_C2 – 22 – CXA3197R (SELE.A mode/SELE.B mode) Clock input pin C2 input pin DA0 to DA9 A8 DB0 to DB9 B7 A6 CXA3197R Select ...
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... Latch MUX Latch Tpw1 Tpw0 0 td-DIV tm 2T- 2.0V 0.8V – 23 – Latch DAC tdo CLK Analog output t tdo SET CXA3197R Analog out tdo ±1/2LSB ±1/2LSB ...
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... The frequency of the clock is halved by the built-in clock frequency divider circuit. CLK/2 can be reset by the reset signal CLK (Internal) Input Latch A MUX Input Latch tdo N – 24 – DAC Latch tdo CXA3197R Analog out ...
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... DIV2IN, are provided simultaneously. These signals are internally multiplexed and the resulting signal can be analog output CLK (Internal) Latch MUX Latch tdo N – 25 – DAC Latch tdo CXA3197R Analog out ...
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... When and Data A is selected for and Data B is selected for Latch Input Latch A Select Input Latch th- SELE. A tdo N N – 2 – 26 – DAC Latch t ( ts- SELE. B tdo CXA3197R Analog out ...
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... VBB – 27 – the reference. CC 0V(A) 0V( VSET –5V(A) VREF 34 –5V(A) AGND2 33 0V(A) AOUTP 32 AOUTN 0V( 0V( 0V( –5V(D) DGND2 25 CXA3197R R L 0V(A) ...
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... All TTL input pins of the CXA3197R except for the PS pin go to High level when left open, and only the PS pin goes to Low level when left open. Set the PS pin to High level to operate the IC. ...
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... Output zero offset voltage vs. Ambient temperature Multiplying bandwidth 10 V pin input frequency [MHz] SET – 29 – AGND2 + 937.5mW SET – – Ambient temperature [° AGND2 + 937.5mW SET – – Ambient temperature [°C] 100 CXA3197R ...
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... NOTE: Dimension “ ” does not include mold protrusion. DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT LQFP-48P-L01 LQFP048-P-0707 LEAD MATERIAL PACKAGE MASS – 30 – + 0.05 0.127 – 0.02 0.1 EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 0.2g CXA3197R ...