CXA3286 Sony Corporation, CXA3286 Datasheet
CXA3286
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CXA3286 Summary of contents
Page 1
... Flash A/D Converter Description The CXA3286R is an 8-bit high-speed flash A/D converter capable of digitizing analog signals at the maximum rate of 160MSPS. ECL, PECL or TTL can be selected as the digital input level in accordance with the application. The TTL digital output level allows 1: 2 demultiplexed output. ...
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... DGND3 1 – 2.0 0 DGND1 DV 1 DGND1 + 2.4 CC 0.4 0.8 125 160 +75 –20 DGND3 V (max (DGND3 – 1.2V (min.) IL CXA3286R Max. +5.25 V +0.05 V +0.05 V –4. +4.1 V +2.6 V 2.1 V DGND3 V V – MSPS MSPS +75 °C ...
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... DGND1 or open or DVcc1 DGND1 or open or DVcc1 Clamp voltage TTL +5V 0V TTL 0V +5V +5V 0V TTL 0V +5V TTL TTL TTL TTL PECL PECL – 3 – CXA3286R Typical voltage level with dual power supply –5.0V 1.4 to 2.6V 0V — + — +5V — 0V 2.9 to 4.1V 0V ECL ECL ...
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... DGND3 (MSB) 40 PBD7 39 PBD6 PBD5 38 PBD4 37 36 PBD3 35 PBD2 PBD1 34 33 PBD0 (LSB) (MSB) PAD7 28 PAD6 27 PAD5 26 25 PAD4 PAD3 24 PAD2 23 PAD1 22 21 PAD0 (LSB) SELECT2 16 VOCLP CLKOUT DGND2 CXA3286R ...
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... TTL output high level clamping The TTL high level voltage is clamped to the value almost 3k equivalent to the voltage applied to this pin . 17 Even if this pin is left open, the TTL high level is clamped to 3.5k DGND2 approximately 2.8V. – 5 – CXA3286R Description ...
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... DGND1 – 6 – CXA3286R Description Power saving. When left open, this pin goes to high level. When set to low level, the power saving state is established. Clock input. CLK/E complementary input. When left open, this pin goes to the threshold voltage. ...
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... Analog input. Vref Port A side data output. TTL output; the high level is clamped to approximately 2.8V. 2 Port B side data output. TTL output; the high level clamped to approximately 2.8V Clock output. (See Table 2. Operation Mode 3 Table.) TTL output; the high level is clamped to approximately 2.8V. CXA3286R ...
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... EE IH – DGND3 1.2 –50 20 –50 20 2.0 0.8 1.5 –10 –20 2.4 0.5 160 10 1.2 1.3 1.5 2.5 2.9 1.0 –0.5 = 5pF) 3.0 4.0 6 5pF 0.5 = 5pF) 3.5 4.5 7.0 = 5pF 5pF) 1 CXA3286R Unit bits LSB LSB pF kΩ µA Ω – 0 µA µ µA 0 µ MSPS ...
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... and – 9 – CXA3286R Min. Typ. Max. Unit MHz 250 – TPS – TPS – TPS 108 140 ...
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... Table 1. I/O Correspondence Table INV – 10 – CXA3286R ...
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... Taj is: ∆ 256 Taj = / = / ( ) 2 f ∆ Comparator Latch CXA3286R 8 Logic Analizer 1024 samples (LSB) Pulse Counter ...
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... When using the multiple CXA3286R in DMUX mode, the start timing of the 1/2 frequency-divided clocks becomes out of phase, producing operation such as that shown in the example on the next page countermeasure, the CXA3286R has a function that resets the 1/2 frequency-divided clocks ...
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... TTL 0V Table 3. Logic Input Level and Power Supply Settings Description of SELECT2 pin The CXA3286R has two systems of data outputs and the port where the data is output can be selected by the SELECT2 pin. SELECT2 pin PA and PB both sides output possible Open PA side output possible; PB side in high impedance Vcc1 PB side output possible ...
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... PAD0 to PAD7 8 bit Digital Data +5V (D) – 14 – CXA3286R 8 bit Digital Data Latch 8 bit Digital Data Latch 8 bit Digital Data Latch 8 bit Digital Data Latch 8 bit Digital Data Latch 8 bit Digital Data ...
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... PECL TTL DG DG +5V (D) +5V ( PAD0 to PAD7 8 bit Digital Data 25 DG +5V (D) +5V (D) – 15 – CXA3286R 8 bit Digital Data Latch 8 bit Digital Data Latch 8 bit Digital Data Latch ...
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... Also important to suppress the noise generated during the TTL output circuit is operating. Place C at the fixed position between the pins with the shortest distance. – 16 – RESETN/E 47 RESET/E 46 RESETN/T 45 SELECT1 44 INV CLKOUT DGND2 41 PBD7 40 PBD6 39 PBD5 38 37 PBD4 CXA3286R ...
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... CLK OUT (Pin 43) T_rh T_rs T_rh RESETN (Pin 48 Td_clk; 4.0ns (typ.) 6.5ns (max) 3.0ns (min) 2.0V 2.0V (Reset period) 0.8V 0.8V T_rs – 17 – CXA3286R Tdo2; 4.5ns (typ.) 3.5ns (min) 7.0ns (max) 2. 0.8V 2. 0.8V Tdo1 0.5ns (typ.) 2.0V 0.8V ...
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... PAD0 to D7 2.0V N – 4 (Pin 21 to 28) 0.8V PBD0 to D7 2.0V N – 3 (Pin 33 to 40) 0.8V Td_clk; 4.0ns (typ.) 3.0ns (min) 6.5ns (max) CLK OUT 2.0V (CLK is inverted and output.) 0.8V (Pin 43 Tpw0 N – – – – 1 – 18 – CXA3286R – ...
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... Notes on Operation • The CXA3286R has the PECL and TTL input pins for the clock and reset input pins. When the clock is input in PECL level, inputting the reset signal in PECL level is recommended. Also, when the clock is input in TTL level, inputting the reset signal in TTL is recommended. ...
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... When the digital input level is ECL or PECL level, the digital input level is TTL, • The CXA3286R TTL output high level is clamped to approximately 2 the IC.This makes it possible to directly interface with the 3.3V system CMOS IC. However,the CXA3286R has the VOCLP pin which is used to clamp the TTL output high level ...
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... Current consumption vs. Conversion rate characteristics f CLK fin = – 1kHz 4 DMUX mode C = 5pF – Conversion rate [MSPS] Reference current vs. Ambient temperature characteristics 25 Ta – Ambient temperature [°C] CXA3286R 160 75 ...
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... Error > 16LSB –7 10 –8 10 –9 10 120 – Conversion rate [MSPS] TTL output high level vs. VOCLP pin 3 –8 10 TPS – 22 – CXA3286R – 1kHz 140 160 180 TTL high level when VOCLP is open VOCLP pin voltage [V] ...
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... LQFP (PLASTIC) 7.0 ± 0 (0.22 0.08 0.13 M 0.1 ± 0.1 NOTE: Dimension “ ” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT LQFP-48P-L01 LQFP048-P-0707 LEAD MATERIAL PACKAGE MASS – 23 – 0.05 0.127 – 0.02 + 0.2 1.5 – 0.1 0.1 S EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 0.2g CXA3286R ...