CXA3572 Sony Corporation, CXA3572 Datasheet

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CXA3572

Manufacturer Part Number
CXA3572
Description
Driver/Timing Generator for Color LCD Panels
Manufacturer
Sony Corporation
Datasheet

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Description
LCD panel ACX306/312.
circuits and parts by incorporating a RGB driver and
timing generator for video signals and a VCO onto a
single chip. This chip has a built-in serial interface
circuit and electronic attenuators which allow various
settings to be performed by microcomputer control,
etc.
Features
• Color LCD panel ACX306/312 driver
• Supports NTSC and PAL systems
• Supports Y/color difference and RGB inputs
• Supports OSD input
• Power saving function (clock stopped)
• Various setting control using a serial interface
• Electronic attenuators (D/A converter)
• VCO (no external oscillator circuit)
• LPF (fc variable)
• COMMON and PSIG output circuits
• Sharpness function
• 2-point correction circuit
• R, G, B signal delay time adjustment circuit
• Sync separation circuit
• D/A output pin (0 to 3V, 8 level output)
• Output polarity inversion circuit
• Supports AC drive for LCD panel during no signal
Applications
The CXA3572R is an IC designed to drive the color
This IC greatly reduces the number of peripheral
circuit (asynchronous type)
Compact LCD monitors, etc.
Driver/Timing Generator for Color LCD Panels
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
• Analog input pin voltage
• Digital input pin voltage
• Common input pin voltage
• Operating temperature
• Storage temperature
• Allowable power dissipation (Ta
Operating Conditions
• Supply voltage
VINA1 (Pins 18, 19, 20, 22, 23, 24 and 25)
VINA2 (Pin 16)
VIND (Pins 34 and 35) V
VINAD (Pins 31, 32 and 33)
CXA3572R
48 pin LQFP (Plastic)
V
V
V
CC
CC
DD
1 – GND1
2 – GND2 11.0 to 14.0
– V
GND – 0.3 to V
GND – 0.3 to V
GND, V
SS
V
V
V
Topr
Tstg
P
CC
CC
DD
D
1
2
SS
– 0.3 to +5.5
SS
–55 to +150
–15 to +75
25°C)
2.7 to 3.6
2.7 to 3.6
– 0.3 to +5.5 V
600
5.5
4.6
15
E00Y05A11-PS
CC
CC
1 + 0.3 V
2 + 0.3 V
mW
°C
°C
V
V
V
V
V
V
V

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CXA3572 Summary of contents

Page 1

... Driver/Timing Generator for Color LCD Panels Description The CXA3572R designed to drive the color LCD panel ACX306/312. This IC greatly reduces the number of peripheral circuits and parts by incorporating a RGB driver and timing generator for video signals and a VCO onto a single chip. This chip has a built-in serial interface ...

Page 2

... Block Diagram ATT 25 ATT ATT RPD 30 31 SEN 32 SCK 33 SDAT SERIAL I PLL 35 XCLR COUNTER 36 POF PICTURE H. FILTER – 2 – CXA3572R ...

Page 3

... SDAT I Serial data input Vertical sync signal input 35 XCLR I Power-on reset capacitor connection (timing output block) LCD panel power supply on/off 36 POF O (Leave this pin open when not using this function.) Description – 3 – CXA3572R Input pin for open status L ...

Page 4

... H clock pulse 1 output 43 HCK2 O H clock pulse 2 output 44 HST O H start pulse output 45 V — Digital 3.0V power supply DD 46 WIDE O WIDE pulse output 47 DWN O Up/down inversion switching signal output 48 V — Digital 3.0V GND SS Description – 4 – CXA3572R Input pin for open status ...

Page 5

... The DC level is controlled to match the SIG.C pin voltage. Low output in power saving mode. Analog 12.0V power supply and PSIG output DC voltage setting. Connect a 0.01µF capacitor between this pin and GND1. When using a SIG.C of other than Vcc2/2, input the SIG.C voltage from an external source. No connection. CXA3572R ...

Page 6

... Sync separation circuit input, or composite sync/horizontal sync signal input. During input to the sync separation circuit, input via a capacitor. DA output. Outputs the serial data converted to DC voltage. The current driving capacity is ±1.0mA (max.). REF output. The current driving capacity (sink) is 1.6mA (max.). CXA3572R ...

Page 7

... GND side of the external resistor and the GND1 pin as close as possible. Phase comparator output. Analog 3.0V GND. Serial clock, serial load and serial data inputs for serial communication. CXA3572R ...

Page 8

... Vss 34 Vss – 8 – Description Digital block outputs. Digital block system reset, and serial clock, serial load and serial data inputs for serial communication. Vertical sync signal input. Digital 3.0V power supply. Digital 3.0V GND. Test. Leave this pin open. CXA3572R ...

Page 9

... In the condition without sync input, adjust so that the HDO pulse output frequency is NTSC: 15.734 ± 0.1kHz and PAL: 15.625 ± 0.1kHz. Setting 3. Canceling power saving mode The power-on default is power saving mode, so clear (set all “1”) serial data PS0 and SYNC GEN > 10µ System reset – 9 – CXA3572R ...

Page 10

... BLACK-LIMITER (100000/LSB) PICTURE-F0 (000/LSB) TRAP DA (000/LSB) (0) INPUT SYNC SEL (0) SEL (1) SLPOF SYNC PONF TEST1 (0) (0) GEN (1) (1) SLWD SLRGT TEST3 (0) (0) (0, 0) SLCLP1 SLCLP0 SLVDO SL4096 (0) (0) (0) (0) H POSITION (100000/LSB) HDO POSITION (00000/LSB) V POSITION (01000/LSB) CXA3572R LSB D0 MODE (0) PS0 (1) SLNTPL (0) SLHDO (0) ...

Page 11

... V16 V22 During Y/color difference V23 input V23 During RGB input During Y/color difference V24 input V24 During RGB input V25 During no input V27 V28 VSIG.C – 11 – CXA3572R 2 = 12.0V, see page 10 for the DAC) CC Min. Typ. Max 1.0 3 1.0 3.4 10 — ...

Page 12

... SYNC level of Y (G) on SYNC signal. Symbol Measurement conditions INPUT SEL = 0 2 (–6dB Attenuate OFF) INPUT SEL = 1 2 (–6dB Attenuate ON) 1 INPUT SEL = 0 (–6dB Attenuate OFF INPUT SEL = 1 (–6dB Attenuate ON) 2 – 12 – CXA3572R Min. Typ. Max. Unit 0.35 0.4 0.15 0.2 0.245 0.311 0.7 0.3 Vp-p 0.490 0.622 0.35 0.5 ...

Page 13

... –1.2mA 4.0mA –0.6mA 2.0mA OL OL – 13 – Min. Typ. Max. Unit 1 – 0 0 150 µA 1.0 1.0 1.0 2.6 0.3 V 2.6 0.3 CXA3572R = 2.7 to 3.6V) Applicable pins (pull-down ...

Page 14

... DC voltage as V 3Fh respectively. – 14 – = 0V, SW8/10/12/14 = OFF, no video input, Min. Typ –6 –3 — — — — –4 –2.0 1.0 2.0 –2.0 –1.4 0.9 1.4 — — — 2.5 1 and 4.5 5.0 CXA3572R Max. Unit ±0.4 dB 0.6 –1.0 dB 4.0 –0.9 V 2.0 100 mV 3.0 V — ...

Page 15

... Input SG4 (160mVp-p) to TP23 and COLOR TP24, and assume the output 00h amplitude at TP8 and TP10 when COLOR = 00h, 40h and 50h as V1, V2 and V3, respectively. COLOR GC1 = 20 log (V1/V2) 50h GC2 = 20 log (V3/V2) – 15 – CXA3572R Min. Typ. Max. Unit 0.3 0.6 1.0 V — — 300 mV 5 ...

Page 16

... Min. Typ. 0.85 1.00 0.41 0.51 0.15 0.19 — 1.5 — 5.2 — –27 5.5 — 1.3 1.5 Output current — — 1.0mA Output current 2.6 — –1.0mA — — 100 — CXA3572R Max. Unit 1.15 0.61 0.23 — MHz — dB –18 MHz — V 1.7 0.3 V — IRE — ...

Page 17

... DWN, WIDE, VCK, VST, TEST, EN, VDO, HDO, POF and RGT output pins (See Fig. 1.) Measure HCK1/HCK2. 120pF load (See Fig. 2.) Measure the HCK1/HCK2 duty. 120pF load – 17 – CXA3572R Min. Typ. Max. Unit 100 — — IRE — — 50 – ...

Page 18

... D14 D13 D12 D11 D10 SDAT ts1 th1 SCK tw1H SEN ts0 Fig. 3. Serial transfer block measurement conditions 90% 10% tTHL Fig. 2. Cross-point time difference tw1L – 18 – CXA3572R T T measurement conditions D15 50% 50% th0 tw2 50% ...

Page 19

... Sine wave video signal; frequency and amplitude variable SG3 25µs SG4 SG5 Waveform 4.7µ 10µs 10µs 25µs – 19 – CXA3572R 3.0Vp-p Amplitude variable Horizontal sync signal 0.1Vp-p 0.1Vp-p High level variable 0V Horizontal sync signal 3V Low level variable Horizontal sync signal ...

Page 20

... SG No. Horizontal sync signal (CSYNC) SG6 Sine wave video signal SG7 Horizontal sync signal (CSYNC) SG8 Waveform 4.7µ 4.7ns 1H – 20 – CXA3572R 50mVp-p 0.1Vp-p 0.15Vp-p ...

Page 21

... TP23 R/R-Y 23 0.01µ TP22 22 G/Y Vcc1 21 0.01µ TP20 OSD G 20 TP19 19 OSD R TP18 OSD SIG.C 0.1µ PSIG DC DET 15 10 Buffer PSIG 14 OUT SW14 +12V 0.01µ TP10 TP12 CXA3572R +3V A 47µ TP16 0.01µ TP14 60n 47µ ...

Page 22

... The G signal is input to Pins 22 and 25, the B signal to Pin 24, and the R signal to Pin 23. the R-Y signal to Pin 23. The G signal is input to Pin 22, the B signal to Pin 24, the R signal to Pin 23, CSYNC/HD to Pin 25, and VD to Pin 34. to Pin 23, CSYNC/HD to Pin 25, and VD to Pin 34. – 22 – CXA3572R correction, 1/3) and Vth2 (Vcc1 2/3). ...

Page 23

... Through Through Through Output Input Fig. 2 – 23 – CXA3572R HCK1 SH1: R signal SH pulse SH2: G signal SH pulse SH3: B signal SH pulse SH4: RGB signal SH pulse SHS1 Serial data settings Output Input ...

Page 24

... BLACK-LIMITER level at some timings. In addition, the RGB output also simultaneously goes to BLACK-LIMITER level output. RGB IN 1H inverted signal (internal) Black frame display signal (internal) PSIG OUT RGB OUT Set by BLACK-LIMITER Set by PSIG-BRIGHT Set by BLACK-LIMITER – 24 – CXA3572R BLACK-LIMITER SIG.C BLACK-LIMITER BLACK-LIMITER WHITE-LIMITER SIG.C WHITE-LIMITER BLACK-LIMITER ...

Page 25

... The serial data PS0 and SYNC GEN must be set in order to use this IC. For details of the setting methods, see the “Description of Serial Control Operation” and “Power supply and power saving sequence” items. Min: 25MHz Max: 30MHz VCO-Fine setting range (255 steps) – 25 – CXA3572R VCO-Coarse setting (7 steps) ...

Page 26

... Power supply and power saving sequence Power-on for the CXA3572R and the LCD panel should be performed in the following order. Power-on LCD V DD (LCD panel 12V (analog 12V block (analog 3V block (digital 3V block) Power saving setting Power saving (serial control) ...

Page 27

... AC driving of LCD panels during no signal The output signal runs freely so that the LCD panel is AC driven even when there is no sync signal from the SYNC IN (Pin 25) and VD (Pin 34) pins. Black display 453 dots 6 lines Display area 228 lines 6 lines Black frame display – 27 – CXA3572R ...

Page 28

... IC and is ignored bits or more of SCK are input, the 16 bits of data before the rising edge of the SEN pulse are valid data. SDAT SCK SEN > 10µs R System reset Serial transfer timing – 28 – CXA3572R A: ADDRESS D: DATA ...

Page 29

... BLACK-LIMITER (100000/LSB) PICTURE-F0 (000/LSB) TRAP DA (000/LSB) (0) INPUT SYNC SEL (0) SEL (0) TEST1 SLPOF SYNC PONF (0) (0) GEN (0) (0) SLWD SLRGT TEST3 (0) (0) (00) SLCLP1 SLCLP0 SLVDO SL4096 (0) (0) (0) (0) H POSITION (100000/LSB) HDO POSITION (00000/LSB) V POSITION (01000/LSB) CXA3572R LSB D0 MODE (0) PS0 (0) SLNTPL (0) SLHDO (0) ...

Page 30

... This adjusts the phase during Y/color difference input. Adjustment from LSB MSB increases the amplitude MSB decreases the amplitude MSB increases the output voltage. MSB increases the gain. MSB advances the phase. – 30 – CXA3572R MSB decreases the LSB lowers the MSB lowers the ...

Page 31

... See the AC Characteristics for the output level (RGB input/no load/typ 1.5MHz 2.1MHz 2.7MHz 3.5MHz 4.1MHz 4.6MHz 5.2MHz — – 31 – CXA3572R MSB increases the MSB increases the MSB lowers the MSB raises the gain. ...

Page 32

... Power saving 1 Normal operation MSB raises the output voltage level. Input signal level 0.35Vp-p or less, 0.5Vp-p or less with sync 0.35Vp-p or more, 0.5Vp-p or more with sync Input connection method Input via a coupling capacitor Input level 3Vp-p positive or negative polarity – 32 – CXA3572R ...

Page 33

... This switches the time until the picture is displayed after power saving is canceled. PONF Mode 0 12 fields 1 4 fields • TEST2 (Default: 0) This is the test mode. Set to “1”. TEST2 Mode 0 Test mode 1 Normal operation • SLNTPL (Default: 0) This switches between NTSC and PAL mode. SLNTPL Mode 0 NTSC 1 PAL – 33 – CXA3572R ...

Page 34

... External VSYNC input • SLSYP (Default: 0) This switches the input sync signal polarity. When performing sync separation with the internal sync separation circuit from YonSYNC or GonSYNC, set this to “0”. SLSYP HD/CSYNC, VSYNC polarity 0 Positive polarity 1 Negative polarity Setting Setting – 34 – CXA3572R ...

Page 35

... SLFR (Default: 0) This function inverts the and PSIG output signal polarities every field. Normally set to 1H inversion. SLFR Polarity inversion cycle 0 1H inversion 1 1-field inversion Position 2.0µs 2.9µs 2.0µs 2.0µs 3.6µs 2.0µs – 35 – CXA3572R ...

Page 36

... These set the HDO pulse output position. The HDO pulse output position is adjusted using the horizontal sync signal as the reference. Adjustment is possible in 1 bit = 4fH increments. HSYNC HDO 30 steps (fH) 31 steps (fH) 31 steps (124fH) – 36 – CXA3572R HP: 100000 (LSB) Default HP: 000000 (LSB) HP: 111111 (LSB) HP: 00000 (LSB) Default HP: 11111 (LSB) ...

Page 37

... This is the test mode. Set to 00000000/LSB (8 bits). 8 steps (8H) 23 steps (23H) SHS1 SHS2 SHS3 SHS4 SHS5 SHS6 (3fH) – 37 – VP: 01000 (LSB) Default VP: 00000 (LSB) VP: 11111 (LSB) SBP: 000 (LSB) SBP: 100 (LSB) SBP: 111 (LSB) 4 steps 3 steps (4fH) (3fH) CXA3572R ...

Page 38

... G/Y G/Y 21 Vcc1 0.1µ 20 OSD G 19 OSD R 33µ 18 OSD 0.01µ SIG.C 16 0.68µ PSIG DC DET 15 Buffer PSIG 14 OUT 0.1µ 33µ 22k 10 IN 22k PSIG Buffer Circuit CXA3572R +3V (Analog) To LCD Panel +12V (Analog) +12V (Analog) 10 OUT ...

Page 39

... The voltages applied to the power supply pins should be as follows GND1 = GND2 (13) Be sure to connect the damping resistor pattern in order to reduce impedance as much as SS (max.) or less.) or lower than V to I/O pins ROUT, GOUT, BOUT, PSIGOUT and COM output. – 39 – CXA3572R should not be SS ...

Page 40

... M 0.1 ± 0.1 0.18 ± 0.03 DETAIL B: PALLADIUM NOTE: Dimension “ ” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL LQFP-48P-L01 LEAD TREATMENT P-LQFP48-7x7-0.5 LEAD MATERIAL PACKAGE MASS – 40 – 0.05 0.127 – 0.02 0.1 S EPOXY RESIN PALLADIUM PLATING COPPER ALLOY 0.2g Sony Corporation CXA3572R ...

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