HY628400A-LLT2-55 Hynix Semiconductor, HY628400A-LLT2-55 Datasheet - Page 8

• Manufacturer Part Number: HY628400A-LLT2-55
• Description: 512K x8 bit 5.0V Low Power CMOS slow SRAM
• Manufacturer: Hynix Semiconductor

Notes:
1. A write occurs during the overlap of a low /WE and a low /CS.
2. tWR is measured from the earlier of /CS or /WE going high to the end of write cycle.
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the
4. If the /CS low transition occur simultaneously with the /WE low transition or after the
5. Q(data out) is the same phase with the write data of this write cycle.
6. Q(data out) is the read data of the next address.
7. Transition is measured + 200mV from steady state.
8. /CS in high for the standby, low for active
DATA RETENTION ELECTRIC CHARATERISTIC
T
Symbol
V
I
tCDR
tR
Notes:
1. Typical values are at the condition of T
2. tRC is read cycle time.
DATA RETENTION TIMING DIAGRAM
Rev 07 / Apr. 2001
CCDR
A
DR
output must not be applied.
/WE transition, outputs remain in a high impedance state.
This parameter is sampled and not 100% tested.
= 0¡ É to 70¡ É ( Normal)/-25 C to 85 C (Extended) /-40 C to 85 C (Industrial), unless otherwise specified.
2.2V
VCC
4.5V
VDR
/CS
VSS
Vcc for Data Retention
Data Retention Current
Chip Deselect to Data
Retention Time
Operating Recovery Time
Parameter
tCDR
DATA RETENTION MODE
/CS > VCC-0.2V
/CS > Vcc - 0.2V,
V
Vcc = 3.0V,
/CS1>Vcc - 0.2V,
V
V
A
IN
IN
IN
= 25 C.
> Vcc - 0.2V or V
> Vcc - 0.2V or
< Vss + 0.2V
Test Condition
tR
IN
< Vss + 0.2V
L
LL
L-E/I
LL-E/I
HY628400A Series
Min
tRC
2.0
(2)
0
-
-
-
-
Typ
-
-
-
-
-
-
-
Max
50
20
50
30
-
-
-
7
Unit
uA
uA
uA
uA
ns
ns
V