IDTIDT71P71604167BQ IDT [Integrated Device Technology], IDTIDT71P71604167BQ Datasheet

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IDTIDT71P71604167BQ

Manufacturer Part Number
IDTIDT71P71604167BQ
Description
Manufacturer
IDT [Integrated Device Technology]
Datasheet
1.IDTIDT71P71604167BQ.pdf (23 pages)
©2006 Integrated Device Technology, Inc. QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc.
Notes
1) Represents 18 signal lines for x18, and 36 signal lines for x36
2) Represents 20 address signal lines for x18 and 19 address signal lines for x36.
3) Represents 2 signal lines for x18 and 4 signal lines for x36.
4) Represents 36 signal lines for x18 and 72 signal lines for x36.
Features
Functional Block Diagram
18Mb Density (1Mx18, 512kx36)
Common Read and Write Data Port
Dual Echo Clock Output
2-Word Burst on all SRAM accesses
Multiplexed Address Bus
DDR (Double Data Rate) Data Bus
Depth expansion through Control Logic
HSTL (1.5V) inputs that can be scaled to receive signals from
1.4V to 1.9V.
Scalable output drivers
1.8V Core Voltage (V
165-ball, 1.0mm pitch, 13mm x 15mm fBGA Package
JTAG Interface
-
-
-
-
BW x
SA
S
R/ W
LD
K
K
C
C
A
Two word bursts data per clock
0
One Read or One Write request per clock cycle
Can drive HSTL, 1.8V TTL or any voltage level
from 1.4V to 1.9V.
Output Impedance adjustable from 35 ohms to 70
ohms
(Note3)
(Note2)
DD
LOGIC
)
CTRL
DATA
GEN
REG
REG
ADD
CLK
(Note2)
SELECT OUTPUT CONTROL
WRITE DRIVER
MEMORY
18Mb Pipelined
DDR™II SRAM
Burst of 2
ARRAY
18M
(Note 1)
1
Description
nous memories with a double-data-rate (DDR), bidirectional data port.
This scheme allows maximization of the bandwidth on the data bus by
passing two data items per clock cycle. The address bus operates at
single data rate speeds, allowing the user to fan out addresses and
ease system design while maintaining maximum performance on data
transfers.
and echo clocks, allowing the user to tune the bus for low noise and high
performance.
beyond SRAM devices that use any form of TTL interface. The inter-
face can be scaled to higher voltages (up to 1.9V) to interface with 1.8V
systems if necessary. The device has a V
allowing the user to designate the interface operational voltage, inde-
pendent of the device core voltage of 1.8V V
control allows the user to adjust the drive strength to adapt to a wide
range of loads and transmission lines.
Clocking
clocks and the C, C clocks. In addition, the DDRII has an output “echo”
clock, CQ, CQ.
(Note1)
The DDRII SRAM has two sets of input clocks, namely the K, K
The IDT DDRII
The DDRII has scalable output impedance on its data output bus
All interfaces of the DDRII SRAM are HSTL, allowing speeds
(Note4)
6112 drw 16
TM
Burst of two SRAMs are high-speed synchro-
(Note1)
CQ
DQ
CQ
IDT71P71804
IDT71P71604
DD.
DDQ
The output impedance
and a separate Vref,
APRIL 2006
DSC-6112/0A

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IDTIDT71P71604167BQ Summary of contents

Page 1

Features 18Mb Density (1Mx18, 512kx36) Common Read and Write Data Port Dual Echo Clock Output 2-Word Burst on all SRAM accesses Multiplexed Address Bus - One Read or One Write request per clock cycle DDR (Double Data Rate) Data Bus ...

Page 2

IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit DDR II SRAM Burst of 2 The K and K clocks are the primary device input clocks. The K clock is used to clock in the control signals (LD, R/W ...

Page 3

IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit DDR II SRAM Burst of 2 Pin Definitions Symbol Pin Function Data I/O signals. Data inputs are sampled on the rising edge of K and K during valid write operations. ...

Page 4

IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit DDR II SRAM Burst of 2 Pin Definitions continued Symbol Pin Function DLL Turn Off. When low this input will turn off the DLL inside the device. The AC timings ...

Page 5

IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit DDR II SRAM Burst of 2 Pin Configuration IDT71P71804 ( ...

Page 6

IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit DDR II SRAM Burst of 2 Pin Configuration IDT71P71604 (512K ...

Page 7

IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit DDR II SRAM Burst of 2 Write Descriptions (1,2,3) Signal 0 BW Write Byte 0 L Write Byte 1 X Write Byte 2 X Write Byte 3 X NOTES: 1) ...

Page 8

IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit DDR II SRAM Burst of 2 Application Example R Data Bus Address LD R MEMORY CONTROLLER Return CLK V t Source CLK ...

Page 9

IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit DDR II SRAM Burst of 2 Absolute Maximum Ratings Symbol Rating Supply Voltage on V with DD V TERM Respect to GND Supply Voltage on V with DDQ V TERM ...

Page 10

IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit DDR II SRAM Burst Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Parameter Symbol Input Leakage Current I IL Output Leakage Current I OL Operating ...

Page 11

IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit DDR II SRAM Burst of 2 Input Electrical Characteristics Over the Operating Temperature and Supply Voltage Range PARAMETER SYMBOL Input High Voltage (DC Input Low Voltage, ...

Page 12

IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit DDR II SRAM Burst Test Conditions (1) Parameter Symbol Core Power Supply Voltage V DD I/O Power Supply Voltage V DDQ Input High Level V IH Input ...

Page 13

IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit DDR II SRAM Burst Electrical Characteristics Symbol Parameter Clock Parameters t Clock Cycle Time (K,K,C,C) KHKH t Clock Phase Jitter (K,K,C,C) KC var t Clock High Time ...

Page 14

IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit DDR II SRAM Burst of 2 Timing Waveform of Combined Read and Write Cycles NOP Read A0 Read A1 (burst of 2) (burst tKHKL ...

Page 15

IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit DDR II SRAM Burst of 2 IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG This part contains an IEEE standard 1149.1 Compatible Test Access Port (TAP). The package pads are ...

Page 16

IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit DDR II SRAM Burst of 2 Scan Register Definition Part Instrustion Register 512K x36 3 bits 1Mx18 3 bits Identification Register Definitions INSTRUCTION FIELD ALL DEVICES Revision Number (31:29) Device ...

Page 17

IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit DDR II SRAM Burst of 2 Boundary Scan Exit Order (1M x 18-Bit) ORDER PIN ...

Page 18

IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit DDR II SRAM Burst of 2 Boundary Scan Exit Order (512K x 36-Bit) ORDER PIN ...

Page 19

IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit DDR II SRAM Burst of 2 JTAG DC Operating Conditions Parameter Symbol I/O Power Supply V DDQ Power Supply Voltage V DD Input High Level V IH Input Low Level ...

Page 20

IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit DDR II SRAM Burst of 2 JTAG AC Characteristics Parameter Symbol TCK Cycle Time t CHCH TCK High Pulse Width t CHCL TCK Low Pulse Width t CLCH TMS Input ...

Page 21

IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit DDR II SRAM Burst of 2 Package Diagram Outline for 165-Ball Fine Pitch Grid Array Commercial Temperature Range 6.42 21 ...

Page 22

IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit DDR II SRAM Burst of 2 Ordering Information IDT 71P71XXX S XXX Device Power Speed Type CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 “QDR SRAMs and ...

Page 23

IDT71P71804 ( -Bit) 71P71604 (512K x 36-Bit DDR II SRAM Burst of 2 Revision History REVISION DATE 0 07/29/05 A 04/21/06 PAGES DESCRIPTION 1-24 Released Final datasheet 1-3,7,8,10,13, Removed 2Mx8 (71P71204) and 2Mx9 (71P71104) device ...

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