TTSV02622V2-DB AGERE [Agere Systems], TTSV02622V2-DB Datasheet
TTSV02622V2-DB
Related parts for TTSV02622V2-DB
TTSV02622V2-DB Summary of contents
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TTSV02622 STS-24 Backplane Transceiver Features Allows wide range of applications for SONET net- work termination application as well as generic data moving for high-speed backplane data transfer. Clock/data recovery (CDR) function for high-speed serial backplane data transfer. CDR function uses ...
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TTSV02622 STS-24 Backplane Transceiver Description (continued STS-24 IN DUAL STS-12 FORMAT DUAL STS-12 Figure 1. Byte Ordering on Input/Output Interface in STS-12 Mode ...
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... Transport Overhead Serial Link ........................................................................................................................... 23 A1/A2 Frame Insert and Corruption ..................................................................................................................... 23 B1 Calculation and Insertion ................................................................................................................................ 23 Stream Disable .................................................................................................................................................... 23 Scrambler............................................................................................................................................................. 23 Receiver Block........................................................................................................................................................ 24 Framer Subblock (Backplane to Line).................................................................................................................. 24 B1 Calculate and Descramble (Backplane to Line) ............................................................................................. 27 Internal Parity Generation .................................................................................................................................... 27 FIFO Subblock (Backplane to Line) ..................................................................................................................... 28 Pointer Mover Subblock (Backplane to Line)....................................................................................................... 28 Miscellaneous Functions ........................................................................................................................................ 31 K1/K2, A1/A2 Handling ...
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... Figure 5. Interior View of TTSV02622 .................................................................................................................... 18 Figure 6. Interconnect of Streams for FIFO Alignment........................................................................................... 19 Figure 7. Transmitter Block .................................................................................................................................... 22 Figure 8. Receiver Block ........................................................................................................................................ 24 Figure 9. Framer State Machine............................................................................................................................. 26 Figure 10. Pointer Mover State Machine ................................................................................................................ 30 Figure 11. LVDS Driver and Receiver and Associated Internal Components ........................................................ 51 Figure 12. LVDS Driver and Receiver .................................................................................................................... 51 Figure 13. LVDS Driver .......................................................................................................................................... 51 Figure 14 ...
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June 2003 Contents Table 1. Pin Assignments for 272-Pin PBGA by Pin Number Order ........................................................................ 7 Table 2. Pin Assignments for 272-Pin PBGA by Signal Name............................................................................... 10 Table 3. Pin Descriptions ....................................................................................................................................... 12 Table 4. Valid Starting Positions for a ...
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TTSV02622 STS-24 Backplane Transceiver Pin Information Figure 2. Pin Diagram of 272-Pin PBGA (Bottom View June 2003 A1 BALL ...
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June 2003 Pin Information (continued) Table 1. Pin Assignments for 272-Pin PBGA by Pin Number Order Pin Signal Name Pin TCK B2 A3 TDI B3 A4 TMS B4 A5 DXP ...
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TTSV02622 STS-24 Backplane Transceiver Pin Information (continued) Table 1. Pin Assignments for 272-Pin PBGA by Pin Number Order (continued) Pin Signal Name Pin E1 STS_INA_P H17 E2 STS_INA_N H18 E3 CTAP_REFA H19 E4 NC H20 E17 NC J1 E18 NC ...
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June 2003 Pin Information (continued) Table 1. Pin Assignments for 272-Pin PBGA by Pin Number Order (continued) Pin Signal Name Pin U1 TSTCLK V1 U2 TSTSHFTLD V2 U3 ETOGGLE TSTMUX3S ...
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TTSV02622 STS-24 Backplane Transceiver Pin Information (continued) Table 2. Pin Assignments for 272-Pin PBGA by Signal Name Signal Name Pin Signal Name BYPASS T2 CPU_ADDR0 Y8 CPU_ADDR1 W8 CPU_ADDR2 V8 CPU_ADDR3 Y7 CPU_ADDR4 W7 DOUTA_C1J1 CPU_ADDR5 V7 DOUTA_PAR CPU_ADDR6 U7 ...
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June 2003 Pin Information (continued) Table 2. Pin Assignments for 272-Pin PBGA by Signal Name (continued) Signal Name Pin Signal Name L18 NC L19 NC L20 NC M20 ...
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TTSV02622 STS-24 Backplane Transceiver Pin Information (continued) Table 3. Pin Descriptions Pin Symbol N18, N19, N20, DINA[7:0] P17, P18, P19, P20, R19 R20 DINA_PAR R18, T17, T18, DINB[7:0] T19, T20, U18, U19, U20 V20 DINB_PAR A15, B15, C15, DOUTA[7:0] A16, ...
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June 2003 Pin Information (continued) Table 3. Pin Descriptions (continued) Pin Symbol B11 TOH_OUTB C11 RX_TOH_CKEN C12 RX_TOH_FP E1 STS_INA_P E2 STS_INA_N F1 STS_INB_P F2 STS_INB_N J1 STS_OUTA_P J2 STS_OUTA_N L1 STS_OUTB_P L2 STS_OUTB_N E3 CTAP_REFA F3 CTAP_REFB U11, V11, ...
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TTSV02622 STS-24 Backplane Transceiver Pin Information (continued) Table 3. Pin Descriptions (continued) Pin Symbol Y9 HIZ_N K1 PLL_REF M1 REF10 M2 REF14 M3 LVDS_RESH M4 LVDS_RESL A5 DXP B6 DXN K2 PLL_VDDA K3 PLL_VSSA A2 TCLK A3 TDI A4 TMS ...
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June 2003 Pin Information (continued) Table 3. Pin Descriptions (continued) Pin Symbol V2 ECSEL W1 EXDNUP U3 ETOGGLE V3 LOOPBKEN W2 TSTPHASE W3, Y3, V4, W4, TSTMUX[8:0]S Y4, U5, V5, W5, Y5 A1, D4, D8, D13 D17, H4, ...
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TTSV02622 STS-24 Backplane Transceiver Pin Information (continued) REF10 REF14 Figure 3. Suggested Schematic for 1.0 V and 1.4 V Reference Voltages 16 3.3 V 3.3 V 2. ...
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June 2003 Synchronization The incoming data from the high-speed interface (HSI) can be separated into two STS-12 channels per slice (A and B). Example of TTSV02622 alignment. There is also a provision to allow certain streams to be disabled (i.e., ...
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TTSV02622 STS-24 Backplane Transceiver Architecture (continued) 1 TOH CLK 1 TX TOH CLK ENA 1 TOH INPUT #1 INPUT BUS #1 DATA(8) PARITY(1) 1 TOH INPUT #2 INPUT BUS #2 DATA(8) PARITY(1) 1 SYSTEM FRAME 1 SYSTEM CLOCK (77.76 MHz) ...
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June 2003 Architecture (continued) The alignment FIFO allows the transfer of all data to the system clock. The FIFO sync block allows the system to be configured to allow the frame alignment of multiple slightly varying data streams (see the ...
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... This feature per-channel basis. Framer monitor: — The framer in the receive direction will report loss of frame (LOF interrupt, as well as a LOF count and errored frame count. The LOF interrupt must not be clearable as long as the channel is in the LOF state. In addition, the errored frame count must represent errored frames, and should not increment more than once per frame even if there are multiple errors ...
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June 2003 Test Features Line loopback: — There is a line loopback feature allowing the user to perform a loopback on the line side (per device control). The line frame signal used by the pointer mover is automatically replaced by ...
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TTSV02622 STS-24 Backplane Transceiver Transmit Direction (Line to Backplane) Each TOH insert block receives two byte-wide 77.76 MHz data from the line, which nominally represents two STS-12 streams (A and B). Transport overhead bytes are then optionally inserted into these ...
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June 2003 Transmit Direction (Line to Backplane) Transport Overhead Serial Link The TOH serial links are used to insert TOH bytes into the transmit data. TOH_IN and TOH_CLK_EN get retimed by TOH_CLK in order to meet setup and hold specifications ...
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... CTL) Framer Subblock (Backplane to Line) The framer block takes byte-wide data from the HSI, and outputs a byte-aligned byte-wide stream and 8 kHz sync pulse (asserted one clock before the first A1 byte). The framer algorithm determines the out-of-frame/in-frame sta- tus of the incoming data and will cause interrupts on both an errored frame and an OOF state. ...
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... Framer Subblock (Backplane to Line) Framer State Machine Figure 9 shows the state machine that controls the framer. Since the TTSV02622 is intended for use between ASICs via a backplane, there is only one errored frame state; thus, after two transitions are missed, the state machine goes into the OOF state and there is no SEF or LOF indication. ...
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... Expect A1/A2 means that row/col/STS counter values indicate time for last (twelfth) A1 byte. 26 (continued) EXPECT A1/A2 & FIND A1/A2 IN FRAME EXPECT A1/A2 & FIND A1/A2 EXPECT A1/A2 & !FIND A1/A2 OOF RESET Figure 9. Framer State Machine June 2003 EXPECT A1/A2 & !FIND A1/A2 ERRORED FRAME EXPECT A1/A2 & !FIND A1/A2 Agere Systems Inc. ...
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... AIS-L Insertion on Out of Frame If enabled via the appropriate bit in the AIS_L force on out of frame register, AIS-L is inserted into the received frame by writing all ones for all bytes of the descrambled stream when the framer indicates that an out of frame condition exists. Internal Parity Generation An even parity is generated on all data bytes and is routed in parallel with the data to be checked before the protec- tion switch MUX at the parallel output ...
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TTSV02622 STS-24 Backplane Transceiver Receiver Block (continued) FIFO Subblock (Backplane to Line) The FIFO subblock consists 10-bit FIFO per STS-12. This FIFO will be used to align up to ±154 interlink skew and to ...
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June 2003 Receiver Block (continued) Pointer Mover Subblock (Backplane to Line) Rules for Concatenation. The pointer mover block can correctly process any length of concatenation (multiple of three) as long as it begins on an STS-3 boundary (i.e., STS-1 number ...
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TTSV02622 STS-24 Backplane Transceiver Receiver Block (continued) Pointer Mover Subblock (Backplane to Line) NORM State. This state will begin whenever two consecutive NORM pointers are received. If two consecutive NORM pointers are received, such that both differ from the current ...
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June 2003 Receiver Block (continued) Pointer Mover Subblock (Backplane to Line) There is no restriction on how many or how often increments and decrements are processed. Any received incre- ment or decrement is immediately passed to the generator for implementation ...
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TTSV02622 STS-24 Backplane Transceiver Registers Definition of Register Types The TTSV02622 design contains six structural register elements: SREG, CREG, PREG, IAREG, ISREG, and IEREG. There are no mixed registers in TTSV02622. This means that all bits of a particular register ...
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June 2003 Registers (continued) Register Map Table 6. Register Map * ADDR Reg. DB7 DB6 [6:0] Type 00 SREG 01 SREG 02 SREG 03 CREG 04 CREG 05 CREG † † 06 PREG — — † † 08 CREG — ...
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TTSV02622 STS-24 Backplane Transceiver Registers (continued) Register Map (continued) Table 6. Register Map (continued) * ADDR Reg. DB7 DB6 [6:0] Type 20, 38 CREG HI-Z HI-Z CONTROL OF CONTROL TOH DATA OF OUTPUT PARALLEL OUTPUT BUS 21, 39 CREG Tx ...
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June 2003 Registers (continued) Register Map (continued) Table 6. Register Map (continued) * ADDR Reg. DB7 DB6 [6:0] Type † † 2A, 42 IAREG — — 2B, 43 IAREG AIS AIS INTERRUPT INTERRUPT FLAG FLAG 11 8 † † — ...
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TTSV02622 STS-24 Backplane Transceiver Register Descriptions Table 7. Register Description Address Bit Name (hex) 00 [7:0] FIXED ID MSB 01 [7:0] FIXED ID LSB 02 [7:0] FIXED REV 03 [7:0] SCRATCH PAD 04 [7:0] LOCKREG MSB 05 [7:0] LOCKREG LSB ...
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June 2003 Register Descriptions (continued) Table 7. Register Description (continued) Address Bit Name (hex LVDS LPBK CONTROL 1 STS-12 SELECT [3:2] EXT PROT SW EN (bit 3) EXT PROT SW FUNC (bit TOH FRAME AND ...
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TTSV02622 STS-24 Backplane Transceiver Register Descriptions (continued) Table 7. Register Description (continued) Address Bit Name (hex SERIAL PORT OUTPUT MUX SELECT FOR PARALLEL PORT OUTPUT MUX SELECT FOR [7:4] 0A [4:0] ...
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June 2003 Register Descriptions (continued) Table 7. Register Description (continued) Address Bit Name (hex) 0C [3:0] NUMBER OF CONSECUTIVE A1/A2 ERRORS TO GENERATE [3:0] 4 LINE LPBK CONTROL 5 INPUT/OUTPUT PARALLEL BUS PARITY CONTROL 6 SCRAMBLER/ DESCREAMBLER CONTROL 7 0D ...
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TTSV02622 STS-24 Backplane Transceiver Register Descriptions (continued) Table 7. Register Description (continued) Address Bit Name (hex INT INT [3:2] 4 PER DEVICE INT [7:5] 11 [4:0] ENABLE/MASK REGISTER [7: FRAME OFFSET ...
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June 2003 Register Descriptions (continued) Table 7. Register Description (continued) Address Bit Name (hex) 20 BEHAVIOR IN LOF 1 FORCE AIS-L CONTROL 2 TOH SERIAL OUTPUT PORT PAR ERR INS CMD 3 Rx K1/K2 SOURCE SELECT 4 ...
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TTSV02622 STS-24 Backplane Transceiver Register Descriptions (continued) Table 7. Register Description (continued) Address Bit Name (hex) 22 SOURCE SELECT SOURCE SELECT SOURCE SELECT SOURCE SELECT 4 Tx ...
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June 2003 Register Descriptions (continued) Table 7. Register Description (continued) Address Bit Name (hex) 25 CONCAT INDICATION 1 1 CONCAT INDICATION 4 2 CONCAT INDICATION 7 3 CONCAT INDICATION 10 4 CONCAT INDICATION 2 5 CONCAT INDICATION 5 ...
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TTSV02622 STS-24 Backplane Transceiver Register Descriptions (continued) Table 7. Register Description (continued) Address Bit Name (hex) 28 FIFO ALIGNER THRESHOLD ERROR FLAG 1 RECEIVER INTER- NAL PATH PARITY ERROR FLAG 2 LOF FLAG 3 LVDS LINK B1 PAR- ...
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June 2003 Register Descriptions (continued) Table 7. Register Description (continued) Address Bit Name (hex) 2B AIS INTERRUPT FLAGS 1 1 AIS INTERRUPT FLAGS 4 2 AIS INTERRUPT FLAGS 7 3 AIS INTERRUPT FLAGS 10 4 AIS INTERRUPT FLAGS ...
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TTSV02622 STS-24 Backplane Transceiver Register Descriptions (continued) Table 7. Register Description (continued) Address Bit Name (hex) 2E OVERFLOW FLAGS OVERFLOW FLAGS OVERFLOW FLAGS OVERFLOW FLAGS 12 [7:4] 2F, ...
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June 2003 Register Descriptions (continued) Table 7. Register Description (continued) Address Bit Name (hex) 31 ENABLE/MASK ES OVERFLOW FLAG 1 1 ENABLE/MASK ES OVERFLOW FLAG 4 2 ENABLE/MASK ES OVERFLOW FLAG 7 3 ENABLE/MASK ES OVERFLOW FLAG 10 ...
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TTSV02622 STS-24 Backplane Transceiver Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso- lute stress ratings only. Functional operation of the device is not implied at these or ...
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June 2003 Thermal Characteristics The TTSV02622 6.49 mm die in the 272-pin PBGA (2-layer BGA). For thermal characteristics, the following values should be used 15.38 °C 25.09 °C 31.92 ...
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TTSV02622 STS-24 Backplane Transceiver LVDS I/O The LVDS buffers are compatible with IEEE IEEE document pertained to just the buffer itself; rather they are system-level specifications. LVDS buffers in the TTSV02622 are compliant to all parts of the IEEE 1596.3 ...
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June 2003 LVDS I/O (continued) LVDS DRIVER Figure 11. LVDS Driver and Receiver and Associated Internal Components DRIVER Agere Systems Inc. TTSV02622 STS-24 Backplane Transceiver 100 CENTER TAP EXTERNAL DEVICE PINS INTERCONNECT GPD ...
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TTSV02622 STS-24 Backplane Transceiver LVDS I/O (continued) LVDS Receiver Buffer Capabilities A disabled or unpowered LVDS receiver can withstand a driving LVDS transmitter over the full range of driver oper- ating range, for an unlimited period of time, without being ...
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June 2003 LVDS I/O (continued) Table 16. LVDS Driver dc Data* Parameter Output Voltage High Output Voltage Low Output Differential Voltage Output Offset Voltage Output Impedance, Signal Ended R Mismatch ...
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TTSV02622 STS-24 Backplane Transceiver Clock and Data Recovery (CDR) The following specifications are in reference to the clock and data recovery macro that is used for the backplane interface on the TTSV02622 chip. Input Data 622 Mbits/s scrambled data stream ...
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June 2003 Timing Characteristics All timing numbers are measured relative to 1.5 V. All outputs are driving 35 pF maximum minimum, except DB pins which drive 100 pF. SYS_CLK SYS_FP INPUT BUS Table 20. Input Parallel Port Timing ...
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TTSV02622 STS-24 Backplane Transceiver Timing Characteristics (continued) SYS_CLK SYS_FP PARALLEL DATA INPUT BUS LVDS DATA OUT Table 21. Transmitter Transport Delay Timing Requirements Symbol T Number of Clocks of Delay from Parallel Bus Input to LVDS Output PROP Notes: LVDS ...
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June 2003 Timing Characteristics (continued) SYS_CLK LINE_FP OUTPUT BUS PARITY, SPE, C1J1 PINS Table 22. Output Parallel Port Timing Requirements Symbol T Clock Period P T Clock Low Time L T Clock High Time H T Data Setup Time SU ...
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TTSV02622 STS-24 Backplane Transceiver Timing Characteristics (continued) SYS_CLK PROT_SW_A OUTPUT BUS* A SYS_CLK OUTPUT BUS A & B Table 23. Protection Switch Timing Requirements Symbol T Transport Delay from Latching of PROT_SW_A to Actual Data TR Switch T Transport Delay ...
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June 2003 Timing Characteristics (continued) SYS_CLK SYS_FP INPUT PARALLEL 36 bytes TOH BUS GUARD BAND (4 TOH CLK) TOH_CLK TOH_ CLK_ENA TOH SERIAL INPUT MSBIT( BYTE STS-1 #1 Table 24. Input Serial Port Timing Requirements ...
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TTSV02622 STS-24 Backplane Transceiver Timing Characteristics (continued) INPUT LVDS SERIAL 622 Mbits/s 36 bytes TOH DATA T TRANS_TOH TOH_CLK RX TOH TOH CLK ENA TOH SERIAL OUTPUT MSBIT( BYTE STS-1 #1 Table 25. Output Serial ...
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June 2003 Timing Characteristics (continued) CPU Interface Timing CS_N RD_WR_N ADDR[6:0] DB[7:0] INTERNAL REGISTER (SYS_CLK DOMAIN) T ADDR_MAX T T DAT_MAX, RD_WR_MAX INT_N Table 26. Write Transaction Timing Requirements Symbol T Minimum Pulse Width for CS_N PULSE T Maximum Time ...
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TTSV02622 STS-24 Backplane Transceiver Timing Characteristics (continued) CPU Interface Timing (continued) CS_N RD_WR_N ADDR[6:0] DB[7:0] T ADDR_MAX T RD_WR_MAX Table 27. Read Transaction Timing Requirements Symbol T Minimum Pulse Width for CS_N PULSE T Maximum Time from Negative Edge of ...
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June 2003 Outline Diagram 272-Pin PBGA Dimensions are in millimeters. A1 BALL IDENTIFIER ZONE MOLD COMPOUND PWB 0.36 0.60 0. CENTER ARRAY E FOR THERMAL ...
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... TTSV02622 STS-24 Backplane Transceiver Ordering Information Device Code TTSV02622V2-DB For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www.agere.com E-MAIL: docmaster@agere.com N. AMERICA: Agere Systems Inc., Lehigh Valley Central Campus, Room 10A-301C, 1110 American Parkway NE, Allentown, PA 18109-9138 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & ...