PC16550DVXNOPB National Semiconductor, PC16550DVXNOPB Datasheet

PC16550DVXNOPB

Manufacturer Part Number

PC16550DVXNOPB

Description

PLCC44

Manufacturer

National Semiconductor

Datasheet

1.PC16550DVNOPB.pdf (22 pages)

Specifications of PC16550DVXNOPB

Date_code

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C 1995 National Semiconductor Corporation

PC16550D Universal Asynchronous

Receiver Transmitter with FIFOs

General Description

The PC16550D is an improved version of the original 16450

Universal Asynchronous Receiver Transmitter (UART)

Functionally identical to the 16450 on powerup (CHARAC-

TER mode) the PC16550D can be put into an alternate

mode (FIFO mode) to relieve the CPU of excessive software

overhead

In this mode internal FIFOs are activated allowing 16 bytes

(plus 3 bits of error data per byte in the RCVR FIFO) to be

stored in both receive and transmit modes All the logic is on

chip to minimize system overhead and maximize system ef-

ficiency Two pin functions have been changed to allow sig-

nalling of DMA transfers

The UART performs serial-to-parallel conversion on data

characters received from a peripheral device or a MODEM

and parallel-to-serial conversion on data characters re-

ceived from the CPU The CPU can read the complete

status of the UART at any time during the functional opera-

tion Status information reported includes the type and con-

dition of the transfer operations being performed by the

UART as well as any error conditions (parity overrun fram-

ing or break interrupt)

The UART includes a programmable baud rate generator

that is capable of dividing the timing reference clock input

by divisors of 1 to (2

driving the internal transmitter logic Provisions are also in-

cluded to use this 16

UART has complete MODEM-control capability and a proc-

essor-interrupt system Interrupts can be programmed to

the user’s requirements minimizing the computing required

to handle the communications link

The UART is fabricated using National Semiconductor’s ad-

vanced M

Basic Configuration

TRI-STATE is a registered trademark of National Semiconductor Corp

Can also be reset to 16450 Mode under software control

Note This part is patented

CMOS process

clock to drive the receiver logic The

1) and producing a 16

TL C 8652

clock for

Features

Capable of running all existing 16450 software

Pin for pin compatible with the existing 16450 except

for CSOUT (24) and NC (29) The former CSOUT and

NC pins are TXRDY and RXRDY respectively

After reset all registers are identical to the 16450 reg-

ister set

In the FIFO mode transmitter and receiver are each

buffered with 16 byte FIFO’s to reduce the number of

interrrupts presented to the CPU

Adds or deletes standard asynchronous communication

bits (start stop and parity) to or from the serial data

Holding and shift registers in the 16450 Mode eliminate

the need for precise synchronization between the CPU

and serial data

Independently controlled transmit receive line status

and data set interrupts

Programmable baud generator divides any input clock

by 1 to (2

Independent receiver clock input

MODEM control functions (CTS RTS DSR DTR RI

and DCD)

Fully programmable serial-interface characteristics

False start bit detection

Complete status reporting capabilities

TRI-STATE TTL drive for the data and control buses

Line break generation and detection

Internal diagnostic capabilities

Full prioritized interrupt system controls

5- 6- 7- or 8-bit characters

Even odd or no-parity bit generation and detection

1- 1 - or 2-stop bit generation

Baud generation (DC to 1 5M baud)

Loopback controls for communications link fault

isolation

Break parity overrun framing error simulation

1) and generates the 16

TL C 8652 – 1

RRD-B30M75 Printed in U S A

clock

June 1995

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