SI5310-C-GMR Silicon Laboratories Inc, SI5310-C-GMR Datasheet

SI5310-C-GMR

Manufacturer Part Number

SI5310-C-GMR

Description

Manufacturer

Silicon Laboratories Inc

Datasheet

1.SI5310-C-GMR.pdf (26 pages)

Specifications of SI5310-C-GMR

Lead_time

Pack_quantity

2500

Comm_code

85423990

Current page: 1 of 26
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Features

Complete precision clock multiplier and clock regenerator device:

Applications

Description

The Si5310 is a fully integrated low-power clock multiplier and clock

regenerator IC. The clock multiplier generates an output clock that is an

integer multiple of the input clock. The clock regenerator operates

simultaneously, creating a “clean” version of the input clock by using the

clock synthesis phase-locked loop (PLL) to remove unwanted jitter and

square up the input clock’s rising and falling edges. The Si5310 uses

Silicon Laboratories patented DSPLL

jitter performance while eliminating the analog loop filter found in

traditional PLL designs with a digital signal-processing algorithm.

The Si5310 represents a new standard in low jitter, small size, low power,

and ease-of-use for clock devices. It operates from a single 2.5 V supply

over the industrial temperature range (–40 to 85 °C).

Functional Block Diagram

Rev. 1.3 6/08

RECISION

Performs clock multiplication to one

of two frequency ranges:

150–167 MHz or 600–668 MHz

Jitter generation as low as

0.5 ps

Accepts input clock from

9.4–668 MHz

SONET/SDH systems

Terabit routers

Digital cross connects

CLKIN+

CLKIN–

rms

for 622 MHz output

BUF

REFCLK+

REFCLK–

Phase-Locked

L O C K

DSPLL

Loop

MULTSEL

Optical transceiver modules

Gigabit Ethernet systems

Fibre channel

Regeneration

architecture to achieve superior

Regenerates a “clean”, jitter-

attenuated version of input clock

DSPLL™ technology provides

superior jitter performance

Small footprint: 4 x 4 mm

Low power: 310 mW typical

ROHS-compliant Pb-free

packaging option available

ULTIPLIER

Calibration

Bias Gen

REXT

BUF

CLKOUT+

CLKOUT–

/ R

PWRDN/CAL

MULTOUT+

MULTOUT–

LOL

EGENERATOR

REFCLK+

REFCLK–

REXT

GND

VDD

Ordering Information:

Pin Assignments

20 19 18 17 16

See page 21.

Si5310

GND

Pad

PWRDN

VDD

CLKOUT+

CLKOUT–

VDD

Si5310

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