CY37128P84125JXI

Manufacturer Part NumberCY37128P84125JXI
DescriptionPLCC
ManufacturerCypress Semiconductor Corporation.
CY37128P84125JXI datasheet
 


Specifications of CY37128P84125JXI

Date_code06+  
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[11]
Parameter
t
1.5V
ER(–)
t
2.6V
ER(+)
t
1.5V
EA(+)
t
V
EA(–)
Switching Characteristics
Over the Operating Range
Parameter
Combinatorial Mode Parameters
[13, 14, 15]
t
Input to Combinatorial Output
PD
[13, 14, 15]
t
Input to Output Through Transparent Input or Output Latch
PDL
[13, 14, 15]
t
Input to Output Through Transparent Input and Output Latches
PDLL
[13, 14, 15]
t
Input to Output Enable
EA
[11, 13]
t
Input to Output Disable
ER
Input Register Parameters
t
Clock or Latch Enable Input LOW Time
WL
t
Clock or Latch Enable Input HIGH Time
WH
t
Input Register or Latch Set-up Time
IS
t
Input Register or Latch Hold Time
IH
[13, 14, 15]
t
Input Register Clock or Latch Enable to Combinatorial Output
ICO
[13, 14, 15]
t
Input Register Clock or Latch Enable to Output Through Transparent Output Latch
ICOL
Synchronous Clocking Parameters
[14, 15]
t
Synchronous Clock (CLK
CO
[13]
t
Set-Up Time from Input to Sync. Clk (CLK
S
t
Register or Latch Data Hold Time
H
[13, 14, 15]
t
Output Synchronous Clock (CLK
CO2
Delay (Through Logic Array)
[13]
t
Output Synchronous Clock (CLK
SCS
Clock (CLK
, CLK
0
[13]
t
Set-Up Time from Input Through Transparent Latch to Output Register Synchronous Clock (CLK
SL
CLK
, CLK
, or CLK
1
2
t
Hold Time for Input Through Transparent Latch from Output Register Synchronous Clock (CLK
HL
CLK
, CLK
, or CLK
1
2
Notes:
11. t
measured with 5-pF AC Test Load and t
measured with 35-pF AC Test Load.
ER
EA
12. All AC parameters are measured with two outputs switching and 35-pF AC Test Load.
13. Logic Blocks operating in Low-Power Mode, add t
14. Outputs using Slow Output Slew Rate, add t
SLEW
15. When V
= 3.3V, add t
to this spec.
CCO
3.3IO
Document #: 38-03007 Rev. *E
V
Output Waveform—Measurement Level
X
V
OH
0.5V
0.5V
V
OL
0.5V
V
X
the
V
X
0.5V
(d) Test Waveforms
[12]
Description
[8]
[8]
, CLK
, CLK
, or CLK
) or Latch Enable to Output
0
1
2
3
, CLK
, CLK
, or CLK
0
1
2
, CLK
, CLK
, or CLK
) or Latch Enable to Combinatorial Output
0
1
2
3
, CLK
, CLK
, or CLK
) or Latch Enable to Output Synchronous
0
1
2
3
, CLK
, or CLK
) or Latch Enable (Through Logic Array)
1
2
3
) or Latch Enable
3
) or Latch Enable
3
to this spec.
LP
to this spec.
Ultra37000 CPLD Family
V
X
V
X
V
OH
V
OL
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
) or Latch Enable
ns
3
ns
ns
ns
ns
0
,
ns
0
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