CY37128P84125JXI

Manufacturer Part NumberCY37128P84125JXI
DescriptionPLCC
ManufacturerCypress Semiconductor Corporation.
CY37128P84125JXI datasheet
 


Specifications of CY37128P84125JXI

Date_code06+  
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Switching Characteristics
Over the Operating Range (continued)
Parameter
Product Term Clocking Parameters
[13, 14, 15]
t
Product Term Clock or Latch Enable (PTCLK) to Output
COPT
t
Set-Up Time from Input to Product Term Clock or Latch Enable (PTCLK)
SPT
t
Register or Latch Data Hold Time
HPT
[13]
t
Set-Up Time for Buried Register used as an Input Register from Input to Product Term Clock or
ISPT
Latch Enable (PTCLK)
t
Buried Register Used as an Input Register or Latch Data Hold Time
IHPT
[13, 14, 15]
t
Product Term Clock or Latch Enable (PTCLK) to Output Delay (Through Logic Array)
CO2PT
Pipelined Mode Parameters
[13]
t
Input Register Synchronous Clock (CLK
ICS
Clock (CLK
, CLK
0
Operating Frequency Parameters
f
Maximum Frequency with Internal Feedback (Lesser of 1/t
MAX1
f
Maximum Frequency Data Path in Output Registered/Latched Mode (Lesser of 1/(t
MAX2
1/(t
+ t
), or 1/t
S
H
CO
f
Maximum Frequency with External Feedback (Lesser of 1/(t
MAX3
f
Maximum Frequency in Pipelined Mode (Lesser of 1/(t
MAX4
[5]
or 1/t
)
SCS
Reset/Preset Parameters
t
Asynchronous Reset Width
RW
[13]
t
Asynchronous Reset Recovery Time
RR
[13, 14, 15]
t
Asynchronous Reset to Output
RO
t
Asynchronous Preset Width
PW
[13]
t
Asynchronous Preset Recovery Time
PR
[13, 14, 15]
t
Asynchronous Preset to Output
PO
User Option Parameters
t
Low Power Adder
LP
t
Slow Output Slew Rate Adder
SLEW
t
3.3V I/O Mode Timing Adder
3.3IO
JTAG Timing Parameters
t
Set-up Time from TDI and TMS to TCK
S JTAG
t
Hold Time on TDI and TMS
H JTAG
t
Falling Edge of TCK to TDO
CO JTAG
f
Maximum JTAG Tap Controller Frequency
JTAG
Document #: 38-03007 Rev. *E
[12]
Description
, CLK
, CLK
, or CLK
0
1
2
, CLK
, or CLK
)
1
2
3
SCS
[5]
)
+ t
CO
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
Ultra37000 CPLD Family
Unit
ns
ns
ns
ns
ns
ns
) to Output Register Synchronous
ns
3
[5]
, 1/(t
+ t
), or 1/t
)
MHz
S
H
CO
+ t
),
MHz
WL
WH
[5]
+ t
) or 1/(t
+ t
)
MHz
CO
S
WL
WH
), 1/t
, 1/(t
+ t
), 1/(t
+ t
),
MHz
IS
ICS
WL
WH
IS
IH
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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