CY62256LL70SNXC Cypress Semiconductor Corporation., CY62256LL70SNXC Datasheet

CY62256LL70SNXC

Manufacturer Part Number

CY62256LL70SNXC

Description

SMD-28

Manufacturer

Cypress Semiconductor Corporation.

Datasheet

1.CY62256LL70SNXC.pdf (14 pages)

Specifications of CY62256LL70SNXC

Date_code

06+

Current page: 1 of 14
Download datasheet (459Kb)

Cypress Semiconductor Corporation

Document #: 38-05248 Rev. *F

Features

Note:

1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.

• High speed

• Temperature Ranges

• Voltage range

• Low active power and standby power

• Easy memory expansion with CE and OE features

• TTL-compatible inputs and outputs

• Automatic power-down when deselected

• CMOS for optimum speed/power

• Available in a Pb-free and non Pb-free standard 28-pin

Logic Block Diagram

— 55 ns

— Commercial: 0°C to 70°C

— Industrial: –40°C to 85°C

— Automotive: –40°C to 125°C

— 4.5V – 5.5V

narrow SOIC, 28-pin TSOP-1, 28-pin Reverse TSOP-1

and 28-pin DIP packages

•

198 Champion Court

INPUTBUFFER

DECODER

32K × 8

ARRAY

COLUMN

Functional Description

The CY62256 is a high-performance CMOS static RAM

organized as 32K words by 8 bits. Easy memory expansion is

provided by an active LOW chip enable (CE) and active LOW

output enable (OE) and Tri-state drivers. This device has an

automatic

consumption by 99.9% when deselected.

An active LOW write enable signal (WE) controls the

writing/reading operation of the memory. When CE and WE

inputs are both LOW, data on the eight data input/output pins

(I/O

addressed by the address present on the address pins (A

through A

the device and enabling the outputs, CE and OE active LOW,

while WE remains inactive or HIGH. Under these conditions,

the contents of the location addressed by the information on

address pins are present on the eight data input/output pins.

The input/output pins remain in a high-impedance state unless

the chip is selected, outputs are enabled, and write enable

(WE) is HIGH.

POWER

DOWN

through I/O

•

256K (32K x 8) Static RAM

San Jose

). Reading the device is accomplished by selecting

power-down

) is written into the memory location

CA 95134-1709

feature,

I/O

[1]

Revised August 3, 2006

reducing

•

CY62256

408-943-2600

the

power

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