A3P125-FGG144I Actel, A3P125-FGG144I Datasheet

A3P125-FGG144I

Manufacturer Part Number

A3P125-FGG144I

Description

Manufacturer

Actel

Datasheet

1.A3P125-2FG144I.pdf (136 pages)

Specifications of A3P125-FGG144I

Lead_time

Pack_quantity

160

Comm_code

85423990

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

BOSTOCK HK LIMITED

Part Number:

A3P125-FGG144I

Manufacturer:

Microsemi SoC

Quantity:

10 000

Company:

Meier Automation Equipment Co., Limited

Part Number:

A3P125-FGG144I

Manufacturer:

MICROSEMI/美高森美

Quantity:

20 000

Current page: 1 of 136
Download datasheet (4Mb)

January 2008

Automotive ProASIC3 Flash Family FPGAs

Features and Benefits

High-Temperature AEC-Q100–Qualified Devices

Firm-Error Immune

High Capacity

Reprogrammable Flash Technology

On-Chip User Nonvolatile Memory

High Performance

In-System Programming (ISP) and Security

Automotive ProASIC3 Product Family

ProASIC3 Devices

System Gates

VersaTiles (D-flip-flops)

RAM kbits (1,024 bits)

4,608-Bit Blocks

FlashROM Bits

Secure (AES) ISP

Integrated PLL in CCCs

VersaNet Globals*

I/O Banks

Maximum User I/Os

Package Pins

Note:

• Grade 2 105°C T

• Grade 1 125°C T

• PPAP Documentation

• Only Automotive FPGAs to Offer Firm-Error Immunity

• Can Be Used without Configuration Upset Risk

• 60 k to 1 M System Gates

• Up to 144 kbits of SRAM

• Up to 300 User I/Os

• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS

• Live-at-Power-Up (LAPU) Level 0 Support

• Single-Chip Solution

• Retains Programmed Design when Powered Off

• 1 kbit of FlashROM with Synchronous Interface

• 350 MHz System Performance

• 3.3 V, 66 MHz 64-Bit PCI

• Secure ISP Using On-Chip 128-Bit Advanced Encryption

• FlashLock

VQFP

FBGA

Automotive Process

Standard (AES) Decryption via JTAG (IEEE 1532–compliant)

*Six chip-wide (main) globals and three additional global networks in each quadrant are available.

to Secure FPGA Contents (anti-tampering)

(115°C T

(135°C T

)

A3P060

VQ100

FG144

1,536

60 k

Yes

1 k

A3P125

VQ100

FG144

125 k

3,072

133

Yes

1 k

Low Power

High-Performance Routing Hierarchy

Advanced I/O

Clock Conditioning Circuit (CCC) and PLL

SRAMs

• 1.5 V Core Voltage

• Support for 1.5-V-Only Systems

• Low-Impedance Flash Switches

• Segmented, Hierarchical Routing and Clock Structure

• High-Performance, Low-Skew Global Network

• Architecture Supports Ultra-High Utilization

• 700 Mbps DDR, LVDS-Capable I/Os

• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

• Bank-Selectable I/O Voltages—up to 4 Banks per Chip

• Single-Ended

• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and

• I/O Registers on Input, Output, and Enable Paths

• Hot-Swappable and Cold-Sparing I/Os

• Programmable Output Slew Rate and Drive Strength

• Weak Pull-Up/-Down

• IEEE 1149.1 (JTAG) Boundary Scan Test

• Pin-Compatible Packages across the Automotive ProASIC

• Six CCC Blocks, One with an Integrated PLL

• Configurable

• Wide Input Frequency Range (1.5 MHz up to 350 MHz)

• Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9,

2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X, and LVCMOS

2.5 V / 5.0 V Input

M-LVDS (A3P250 and A3P1000)

Family

Capabilities, and External Feedback

and ×18 organizations available)

FG144, FG256

I/O

Phase

A3P250

VQ100

250 k

6,144

157

Yes

1 k

Standards:

Shift,

LVTTL,

Multiply/Divide,

FG144, FG256, FG484

A3P1000

LVCMOS

24,576

1 M

144

300

Yes

1 k

v1.0

3.3 V /

Delay

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