M36L0R8060B1ZAQE STMICROELECTRONICS [STMicroelectronics], M36L0R8060B1ZAQE Datasheet

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M36L0R8060B1ZAQE

Manufacturer Part Number
M36L0R8060B1ZAQE
Description
256 Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory and 64 Mbit (Burst) PSRAM, 1.8V Supply, Multi-Chip Package
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
FEATURES SUMMARY
FLASH MEMORY
June 2005
and 64 Mbit (Burst) PSRAM, 1.8V Supply, Multi-Chip Package
MULTI-CHIP PACKAGE
SUPPLY VOLTAGE
ELECTRONIC SIGNATURE
PACKAGE
SYNCHRONOUS / ASYNCHRONOUS READ
SYNCHRONOUS BURST READ SUSPEND
PROGRAMMING TIME
MEMORY ORGANIZATION
DUAL OPERATIONS
SECURITY
1 die of 256 Mbit (16Mb x16, Multiple
Bank, Multi-level, Burst) Flash Memory
1 die of 64 Mbit (4Mb x16) Pseudo SRAM
V
V
Manufacturer Code: 20h
Top Device Code
M36L0R8060T1: 880Dh
Bottom Device Code
M36L0R8060B1: 880Eh
Compliant with Lead-Free Soldering
Processes
Lead-Free Versions
Synchronous Burst Read mode: 54MHz
Asynchronous Page Read mode
Random Access: 85ns
10µs typical Word program time using
Buffer Enhanced Factory Program
command
Multiple Bank Memory Array: 16 Mbit
Banks
Parameter Blocks (Top or Bottom
location)
program/erase in one Bank while read in
others
No delay between read and write
operations
64 bit unique device number
2112 bit user programmable OTP Cells
DDF
PPF
256 Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory
= 9V for fast program (12V tolerant)
= V
CCP
= V
DDQF
= 1.7 to 1.95V
Figure 1. Package
PSRAM
BLOCK LOCKING
COMMON FLASH INTERFACE (CFI)
100,000 PROGRAM/ERASE CYCLES per
BLOCK
ACCESS TIME: 70ns
ASYNCHRONOUS PAGE READ
LOW POWER FEATURES
SYNCHRONOUS BURST READ/WRITE
All blocks locked at power-up
Any combination of blocks can be locked
with zero latency
WP
Absolute Write Protection with V
Page Size: 16 words
Subsequent read within page: 20ns
Temperature Compensated Refresh
(TCR)
Partial Array Refresh (PAR)
Deep Power-Down (DPD) Mode
F
for Block Lock-Down
M36L0R8060B1
M36L0R8060T1
TFBGA88 (ZAQ)
8 x 10mm
FBGA
PPF
= V
1/18
SS

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M36L0R8060B1ZAQE Summary of contents

Page 1

Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory and 64 Mbit (Burst) PSRAM, 1.8V Supply, Multi-Chip Package FEATURES SUMMARY MULTI-CHIP PACKAGE – 1 die of 256 Mbit (16Mb x16, Multiple Bank, Multi-level, Burst) Flash Memory – 1 die of 64 ...

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M36L0R8060T1, M36L0R8060B1 TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Table 4. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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... PseudoSRAM, the M69KB096AA. This document should be read in conjunction with the M30L0R8000x0 and datasheets. Recommended operating conditions do not allow more than one memory to be active at the same time. The memory is offered in a Stacked TFBGA88 (8x10mm, 8x10 ball array, 0.8mm pitch) package. ...

Page 5

Table 1. Signal Names A0-A23 Address Inputs DQ0-DQ15 Common Data Input/Output L Latch Enable input for Flash memory and PSRAM K Burst Clock for Flash memory and PSRAM WAIT Wait Data in Burst Mode for Flash memory and PSRAM V ...

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M36L0R8060T1, M36L0R8060B1 Figure 3. TFBGA Connections (Top view through package A18 A17 DQ8 G P DQ0 ...

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... Latch Enable (L). The Latch Enable pin is com- mon to the Flash memory and PSRAM compo- nents. For details of how the Latch Enable signal be- haves, please refer to the datasheets of the re- spective memory components: M69KB096AA for the PSRAM and M30L0R8000T/B0 for the Flash memory. ...

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M36L0R8060T1, M36L0R8060B1 PSRAM Upper Byte Enable (UB Byte En-able gates the data on the Upper P Byte Data Inputs/Outputs (DQ8-DQ15 from the upper part of the selected address during a Write or Read operation. PSRAM Lower ...

Page 9

FUNCTIONAL DESCRIPTION The PSRAM and Flash memory components have separate power supplies but share the same grounds. They are distinguished by two Chip En- able inputs: E for the Flash memory and E F the PSRAM. Recommended operating conditions do ...

Page 10

M36L0R8060T1, M36L0R8060B1 Table 2. Main Operating Modes Operation Flash Read Flash Write Flash Address Latch Flash Output V ...

Page 11

MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause per- manent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above ...

Page 12

M36L0R8060T1, M36L0R8060B1 DC AND AC PARAMETERS This section summarizes the operating measure- ment conditions, and the DC and AC characteris- tics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed ...

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Table 6. Flash Memory DC Characteristics - Currents Symbol Parameter I Input Leakage Current LI I Output Leakage Current LO Supply Current Asynchronous Read (f=5MHz) I DD1 Supply Current Synchronous Read (f=54MHz) Supply Current I DD2 (Reset) I Supply Current ...

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M36L0R8060T1, M36L0R8060B1 Table 7. Flash Memory DC Characteristics - Voltages Symbol Parameter V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage Program Voltage-Logic PP1 ...

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PACKAGE MECHANICAL Figure 7. TFBGA88 8x10mm, 8x10 ball array - 0.8mm pitch, Bottom View Package Outline BALL "A1" FE Note: Drawing is not to scale. Table 9. Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, ...

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M36L0R8060T1, M36L0R8060B1 PART NUMBERING Table 10. Ordering Information Scheme Example: Device Type M36 = Multi-Chip Package (Multiple Flash + RAM) Flash 1 Architecture L = Multilevel, Multiple Bank, Burst mode Flash 2 Architecture Die Operating Voltage R ...

Page 17

REVISION HISTORY Table 11. Document Revision History Date Version 15-Oct-2004 0.1 First Issue 29-Apr-2004 0.2 Part Number M69KB096A changed to M69KB096AA throughout document. Status changed from Preliminary to Full Datasheet. 24-June-2005 0.3 modified. Signal changed from M36L0R8060T1, M36L0R8060B1 Revision Details ...

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M36L0R8060T1, M36L0R8060B1 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from ...

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