M368L3223ETM-CLCC4 SAMSUNG [Samsung semiconductor], M368L3223ETM-CLCC4 Datasheet
M368L3223ETM-CLCC4
Related parts for M368L3223ETM-CLCC4
M368L3223ETM-CLCC4 Summary of contents
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... Unbuffered DIMM DDR SDRAM Unbuffered Module (DDR400 Module) 184pin Unbuffered Module based on 256Mb E-die 64/72-bit ECC/Non ECC Revision 1.3 August. 2003 DDR SDRAM Rev. 1.3 August. 2003 ...
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Unbuffered DIMM Revision History Revision 1.0 (February, 2003) - First release Revision 1.1 (February, 2003) - Modified tAC value +/-0.7ns => +/-0.65ns Revision 1.2 (May, 2003) - Corrected typo Revision 1.3 (August, 2003) - Corrected typo DDR SDRAM ...
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... Unbuffered DIMM 184Pin Unbuffered DIMM based on 256Mb E-die (x8) Ordering Information Part Number M368L3223ETM-C(L)CC/C4 M368L6423ETM-C(L)CC/C4 M381L3223ETM-C(L)CC/C4 M381L6423ETM-C(L)CC/C4 Operating Frequencies Speed @CL3 CL-tRCD-tRP Feature • Power supply : Vdd: 2.6V ± 0.1V, Vddq: 2.6V ± 0.1V • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • ...
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... Note : These pins are not used in this module. 2. Pins 44, 45, 47, 49, 51, 134, 135, 140, 142, 144 are used on x72 module, and are not used on x64 module. 3. Pins 111, 158 are NC for 1 Row Module[M368(81)L3223ETM] & used for 2 Row Moduel[M368(81)L6423ETM] Pin Description ...
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... Unbuffered DIMM 256MB, 32M x 64 Non ECC Module (M368L3223ETM) Functional Block Diagram CS0 DQS0 DM0 DQS DM CS DQ0 I/O 7 DQ1 I DQ2 I/O 1 DQ3 I/O 0 DQ4 I/O 5 DQ5 I/O 4 I/O 3 DQ6 I/O 2 DQ7 DQS1 DM1 DQS CS DM DQ8 I/O 7 DQ9 I DQ10 I/O 1 DQ11 I/O 0 I/O 5 DQ12 I/O 4 DQ13 ...
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... BA0-BA1 : DDR SDRAMs A12 A0-A12 : DDR SDRAMs RAS RAS : DDR SDRAMs CAS CAS : DDR SDRAMs CKE0 CKE : DDR SDRAMs DDR SDRAMs (Populated as 1 bank of x8 DDR SDRAM Module) DQS4 DM4 DM DQS DQ32 I/O 7 DQ33 I/O 6 DQ34 I/O 1 ...
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... I/O 4 I/O 5 Serial PD SCL SA0 SA1 *Clock Net Wiring Ω R=120 CK0/1/2 Card Edge *If four DRAMs are loaded, Cap will replace DRAM DDR SDRAM (Populated as 2 bank of x8 DDR SDRAM Module DQS DM I/O 0 DQ32 I/O 7 I/O 1 DQ33 I I/O 6 DQ34 I/O 1 I/O 7 DQ35 I/O 0 ...
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... CAS CAS : DDR SDRAMs D0 - D17 CKE1 CKE : DDR SDRAMs D9 - D17 CKE0 CKE : DDR SDRAMs DDR SDRAMs D0 - D17 V DDSPD DDQ VREF V SS (Populated as 2 bank of x8 DDR SDRAM Module) CS1 DQS4 DM4 DQS DQS I I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 ...
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Unbuffered DIMM Absolute Maximum Ratings Parameter Voltage on any pin relative to V Voltage on V & V supply relative DDQ Storage temperature Power dissipation Short circuit current Note : Permanent device damage may occur ...
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... Unbuffered DIMM DDR SDRAM IDD spec table M368L3223ETM Symbol CC(DDR400@CL=3) C4(DDR400@CL=3) CC(DDR400@CL=3) C4(DDR400@CL=3) IDD0 840 IDD1 1040 IDD2P 35 IDD2F 240 IDD2Q 200 IDD3P 440 IDD3N 600 IDD4R 1480 IDD4W 1520 IDD5 1440 IDD6 Normal 24 Low power 12 IDD7A 2480 * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. ...
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... CIN1 CIN2 CIN3 CIN4 CIN5 Cout1 Cout2 DDR SDRAM Max Min VREF + 0.31 VREF - 0.31 0.7 VDDQ+0.6 0.5*VDDQ-0.2 0.5*VDDQ+0.2 DDQ R =50Ω REF =0.5*V DDQ (VDD=2.6V, VDDQ=2.6V, TA= 25°C, f=1MHz) M368L3223ETM M381L3223ETM Min Max Min ...
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Unbuffered DIMM AC Timing Parameters and Specifications Parameter Row cycle time Refresh row cycle time Row active time RAS to CAS delay Row precharge time Row active to Row active delay Write recovery time Internal write to read ...
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Unbuffered DIMM Parameter Data hold skew factor Auto Precharge write recovery + precharge time Exit self refresh to non-READ command Exit self refresh to READ command Component Notes 1.V is the magnitude of the difference between the input ...
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Unbuffered DIMM System Characteristics for DDR SDRAM The following specification parameters are required in systems using DDR400 devices to ensure proper system perfor- mance. these characteristics are for system simulation purposes and are guaranteed by design. Table 1 ...
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Unbuffered DIMM System Notes : a. Pullup slew rate is characteristized under the test conditions as shown in Figure 1. Output Figure 1 : Pullup slew rate test load b. Pulldown slew rate is measured under the test ...
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Unbuffered DIMM j. Table 3 is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the lesser on the lesser of the ...
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Unbuffered DIMM Command Truth Table COMMAND Register Extended MRS Register Mode Register Set Auto Refresh Refresh Self Refresh Bank Active & Row Addr. Read & Auto Precharge Disable Column Address Auto Precharge Enable Write & Auto Precharge Disable ...
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... Unbuffered DIMM Physical Dimensions : 32M x 64 (M368L3223ETM), 32M x 72 (M381L3223ETM) PACKAGE DIMENSIONS 1.25 ± 0.006 (31.75 ±0.15) 0.250 (6.350) 0.26 (6.62) 2.175 Detail A Tolerances : ± 0.005(.13) unless otherwise specified. The used device is 32Mx8 DDR SDRAM, TSOPII. DDR SDRAM Part NO : K4H560838E. 5.25 ± 0.006 (133.350 ± 0.15) 5 ...
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Unbuffered DIMM Physical Dimensions : 64M x 64 (M368L6423ETM), 64M x 72 (M381L6423ETM) PACKAGE DIMENSIONS 1.25 ± 0.006 (31.75 ±0.15) 0.250 (6.350) 0.26 (6.62) 2.175 Detail A Tolerances : ± 0.005(.13) unless otherwise specified. The used device is ...