HYS64D128021GBDL-5-B INFINEON [Infineon Technologies AG], HYS64D128021GBDL-5-B Datasheet
HYS64D128021GBDL-5-B
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HYS64D128021GBDL-5-B Summary of contents
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... – 5 – – 6 – B 200-Pin Small Outline Dual-In-Line Memory Modules ...
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Edition 2003-12 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 München, Germany Infineon Technologies AG 2003. © All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of ...
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... – 5 – – 6 – B 200-Pin Small Outline Dual-In-Line Memory Modules ...
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HYS64D128021[G/H]BDL–5–B, HYS64D128021[G/H]BDL–6–B, Revision History: Rev. 0.5 Previous Version: Page Subjects (major changes since last revision) We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us ...
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... Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 Current Specification and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 SPD Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Data Sheet HYS64D128021[H/G]BDL–[5/6]–B Small Outline DDR SDRAM Modules 5 Rev. 0.5, 2003-12 ...
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... The HYS64D128021[G/H]BDL–5–B and HYS64D128021[G/H]BDL–6–B are industry standard 200-Pin Small Outline Dual-In-Line Memory Modules (SO-DIMMs) organized as 128M × 64. The memory array is designed with Double Data Rate Synchronous DRAMs (DDR SDRAM). A variety of decoupling capacitors are mounted on the PC board ...
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... Table 2 Ordering Information Type PC3200 (CL=3) HYS64D128021GBDL–5–B PC2700 (CL=2.5) HYS64D128021GBDL–6–B PC3200 (CL=3) HYS64D128021HBDL–5–B PC2700 (CL=2.5) HYS64D128021HBDL–6–B Note: 1. All part numbers end with a place code designating the silicon-die revision. Reference information available on request. Example: HYS64D32020GDL-6-B, indicating rev. B dies are used for SDRAM components. ...
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... SA0 - SA2 Input; O: Output; I/O: bidirectional In-/Output; AI: Analog Input; PWR: Power Supply; GND: Signal Ground; NC: Not Connected; NU: Not Usable 2) CKE1 and S1 are used on two bank modules only Data Sheet 1) Function Address Inputs Bank Address Data Input/Output Command Input Clock Enable ...
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... SS 53 DQ19 54 DQ23 55 DQ24 56 DQ28 DQ25 60 DQ29 61 DQS3 62 DM3 Data Sheet Small Outline DDR SDRAM Modules Front side Back side Pin # Symbol Pin # Symbol 65 DQ26 66 DQ30 67 DQ27 68 DQ31 (CB0) 72 (CB4) 73 (CB1) 74 (CB5) V ...
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... Table 5 Address Format Density Organization Memory Ranks 128M × 64 1GB 2 Figure 1 Pin Configuration Data Sheet HYS64D128021[H/G]BDL–[5/6]–B Small Outline DDR SDRAM Modules SDRAMs # row/bank/ SDRAMs columns bits 64M × 13/2/11 front side back side 10 Pin Configuration Refresh Period Interval 7.8 µ ...
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... SA0 SA1 SA2 * Clock Wiring Clock SDRAMs Input 4 SDRAMs *CK0/CK0 *CK1/CK1 6 SDRAMs *CK2/CK2 6 SDRAMs * Wire per Clock Loading Table/Wiring Diagrams 11 HYS64D128021[H/G]BDL–[5/6]–B Small Outline DDR SDRAM Modules Pin Configuration DM S DQS DM I/O 0 DQ32 I/O 0 I/O 1 DQ33 I I/O 2 DQ34 I/O 2 I/O 3 DQ35 ...
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... DDQ DDQ V V – 0.04 REF V + 0.15 V REF V –0.3 –0.3 V 0.36 V 0.71 1.4 12 HYS64D128021[H/G]BDL–[5/6]–B Small Outline DDR SDRAM Modules Electrical Characteristics Values Unit Note/ Test typ. max. – DDQ 0.5 – +3.6 V – +3.6 V – +3.6 V °C – +70 °C – ...
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... REF V stabilizes. REF 13 HYS64D128021[H/G]BDL–[5/6]–B Small Outline DDR SDRAM Modules Electrical Characteristics Unit Note/Test Condition µA Any input 0 V ≤ All other pins not under test 8) µA DQs are disabled; ...
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... for DDR266(A for DDR333 and DDR400B Auto-Refresh Current burst refresh RC RFCMIN Self-Refresh Current CKE ≤ 0.2 V; external clock on Operating Current 7 four bank interleaving with Burst Length = 4; see component data sheet. Data Sheet Small Outline DDR SDRAM Modules V IL,MAX V ; IH,MIN for DQ, DQS and DM ...
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... values of the component data sheet as follows: DDx [component] with m and n number of components of rank 1 and 2; n=0 for 1 rank data sheet values as × I DDx 15 HYS64D128021[H/G]BDL–[5/6]–B Small Outline DDR SDRAM Modules Electrical Characteristics 1)2) Unit Note ...
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... DQS falling edge hold time from CK (write cycle) Mode register set command cycle time Write preamble setup time Write postamble Write preamble Data Sheet HYS64D128021[H/G]BDL–[5/6]–B Small Outline DDR SDRAM Modules Symbol –6 DDR333B Min. Max. Min. t –0.7 +0.7 – ...
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... A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on Data Sheet Small Outline DDR SDRAM Modules Symbol –6 DDR333B Min ...
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... OH(ac) 11) For each of the terms, if not already an integer, round to the next highest integer. cycle time. 12) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device. Data Sheet Small Outline DDR SDRAM Modules V . OL(ac) 18 HYS64D128021[H/G]BDL–[5/6]–B Electrical Characteristics ...
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... Burst Length Supported 17 Number of Banks on SDRAM Device 18 CAS Latency 19 CS Latency 20 Write Latency 21 DIMM Attributes Data Sheet HYS64D128021[H/G]BDL–[5/6]–B Small Outline DDR SDRAM Modules 1 GByte 1 GByte ×64 ×64 2 Ranks 2 Ranks PC3200S– PC3200S– 3033–1 3033–1 Rev 1.0 Rev 1.0 HEX ...
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... SPD Revision 63 Checksum of Byte 0-62 64 JEDEC ID Code of Infineon (1) 65 – 71 JEDEC ID Code of Infineon (2 – Data Sheet HYS64D128021[H/G]BDL–[5/6]–B Small Outline DDR SDRAM Modules 1 GByte 1 GByte ×64 ×64 2 Ranks 2 Ranks PC3200S– PC3200S– 3033–1 3033–1 Rev 1 ...
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... Module Revision Code 92 Test Program Revision Code 93 Module Manufacturing Date Year xx 94 Module Manufacturing Date Week xx 95 – 98 Module Serial Number (1 – – 127 not used Data Sheet HYS64D128021[H/G]BDL–[5/6]–B Small Outline DDR SDRAM Modules 1 GByte 1 GByte ×64 × ...
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... Package Outlines (2.15) 1 11.4 ±0.1 (2.45) 1 ±0.1 101 2 MIN. Detail of contacts 0.6 ±0.1 Burnished, no burr allowed Figure 3 Package Outlines – DDR-SDRAM SO-DIMM HYS64D128021[H/G]BDL–[5/6]–B Data Sheet Small Outline DDR SDRAM Modules 67.6 63.6 ±0.1 (2.45) 18.45 ±0.1 1.8 ±0.1 (2.4) 47.4 ±0.1 (2.7) (2.15) 1.5 ±0.1 200 0.45 ±0.03 22 HYS64D128021[H/G]BDL–[5/6]–B Package Outlines 3 ...
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Published by Infineon Technologies AG ...