HYS64D128320HU-5-B QIMONDA [Qimonda AG], HYS64D128320HU-5-B Datasheet - Page 17

• Manufacturer Part Number: HYS64D128320HU-5-B
• Description: 42184-Pin Unbuffered Double-Data-Rate Memory Modules
• Manufacturer: QIMONDA [Qimonda AG]

1) 0 °C ≤
2) Input slew rate ≥ 1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals
4) Inputs are not recognized as valid until
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is
6) These parameters guarantee device timing, but they are not necessarily tested on each device.
7)
8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition
9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system
10) Fast slew rate ≥ 1.0 V/ns, slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured
11) For each of the terms, if not already an integer, round to the next highest integer.
12) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Rev. 1.22, 2007-01
03292006-CXBY-V2JX
Parameter
Address and control input hold time
Read preamble
Read postamble
Active to Precharge command
Active to Active/Auto-refresh command
period
Auto-refresh to Active/Auto-refresh
command period
Active to Read or Write delay
Precharge command period
Active to Autoprecharge delay
Active bank A to Active bank B command
Write recovery time
Auto precharge write recovery + precharge
time
Internal write to read command delay
Exit self-refresh to non-read command
Exit self-refresh to read command
Average Periodic Refresh Interval
other than CK/CK, is
t
voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the
bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from
HIGH to LOW at this time, depending on
performance (bus turnaround) degrades accordingly.
between
HZ
and
T
t
A
LZ
V
≤ 70 °C
IH(ac)
transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific
and
; V
V
DDQ
V
IL(ac)
REF
= 2.5 V ± 0.2 V,
.
. CK/CK slew rate are ≥ 1.0 V/ns.
V
V
REF
t
DQSS
DD
stabilizes.
= +2.5 V ± 0.2 V (DDR333);
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
.
Symbol
IH
RPRE
RPST
RAS
RC
RFC
RCD
RP
RAP
RRD
WR
DAL
WTR
XSNR
XSRD
REFI
–5
DDR400B
Min.
0.6
0.7
0.9
0.40
40
55
70
15
15
t
10
15
—
2
75
200
—
RCD
17
– t
RASmin
Max.
—
—
1.1
0.60
70E+3
—
—
—
—
—
—
—
—
—
—
7.8
V
DDQ
= 2.6 V ± 0.1 V,
t
CK
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
–6
DDR333
Min.
0.75
0.8
0.9
0.40
42
60
72
18
18
12
15
—
1
75
200
—
is equal to the actual system clock cycle time.
Unbuffered DDR SDRAM Modules
Max.
—
—
1.1
0.60
70E+3
—
—
—
—
—
—
—
—
—
—
7.8
V
DD
= +2.6 V ± 0.1 V (DDR400)
Unit
ns
ns
t
t
ns
ns
ns
ns
ns
ns
ns
ns
t
t
ns
t
µs
CK
CK
CK
CK
CK
Internet Data Sheet
Note
Condition
Fast slew rate
3)4)5)6)10)
Slow slew rate
3)4)5)6)10)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)11)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)12)
V
TT
.
1)
/ Test