HYS64T128020EDL-2.5-B QIMONDA [Qimonda AG], HYS64T128020EDL-2.5-B Datasheet - Page 17

• Manufacturer Part Number: HYS64T128020EDL-2.5-B
• Description: 200-Pin Small-Outlined DDR2 SDRAM Modules
• Manufacturer: QIMONDA [Qimonda AG]

5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
6) Inputs are not recognized as valid until
7) The output timing reference voltage level is
8) New units, ‘
9) When the device is operated with input clock jitter, this parameter needs to be derated by the actual
10) Input clock jitter spec parameter. These parameters component datasheet are referred to as 'input clock jitter spec parameters' and these
11) These parameters are specified per their average values, however it is understood that the relationship component datasheet between the
12)
13) DAL = WR + RU{
14)
15) Input waveform timing
16)
17) These parameters are measured from a data strobe signal ((L/U/R)DQS / DQS) crossing to its respective clock signal (CK / CK) crossing.
18) Input waveform timing
19) If
20) These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal
21)
22)
23) input waveform timing is referenced from the input signal crossing at the
24) Input waveform timing is referenced from the input signal crossing at the
25) These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to
26)
Rev. 1.12, 2007-10
10312006-I253-V1V0
input reference level is the crosspoint when in differential strobe mode. component
under operation. Unit ‘nCK‘ represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2–400 and
DDR2–533, ‘
may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has
ps and
t
= - 900 ps – 293 ps = – 1193 ps and
parameters apply to DDR2–667 and DDR2–800 only. The jitter specified is a random jitter meeting a Gaussian distribution.
average timing and the absolute instantaneous timing holds all the times (min. and max of SPEC values are to be used for calculations
component datasheet).
t
entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during
the time period of
of the division is not already an integer, round up to the next highest integer.
DDR2–533 at
t
the input signal crossing at the
at the
V
t
slew rate mismatch between DQS / DQS and associated DQ in any given cycle.
The spec values are not affected by the amount of clock jitter applied (i.e.
crossing. That is, these parameters should be met whether clock jitter is present or not.
to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the
crosspoint for a falling signal applied to the device under test. DQS, DQS signals must be monotonic between
Figure
((L/U/R)DQS / DQS) crossing.
t
It is used in conjunction with t
following equation;
minimum of the actual instantaneous clock low time.
t
which specifies when the device output is no longer driving (
to the device under test. See
to the device under test. See
its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e.
etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should
be met whether clock jitter is present or not.
t
the max column. {The less half-pulse width distortion present, the larger the
Examples: 1) If the system provides
provides
DQSCK.MAX(DERATED)
CKE.MIN
DAL.nCK
DQSQ
HP
HZ
QH
IH.DC.MIN
t
DS
and
is the minimum of the absolute half period of the actual input clock.
=
: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output
or
t
V
HP
t
3.
of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the
= WR [nCK] +
t
IL.DC
ERR(6- 10PER).MAX
t
LZ
DH
. See
–
t
HP
transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level
t
t
is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed.
QHS
CK.AVG
level for a rising signal applied to the device under test. DQS, DQS signals must be monotonic between
of 1420 ps into a DDR2–667 SDRAM, the DRAM provides
t
CK
t
CK
Figure
, where:
‘ is used for both concepts. Example:
t
RP
= 3.75 ns with
t
‘ and ‘nCK‘, are introduced in DDR2–667 and DDR2–800. Unit ‘
=
IS
t
(ns) /
HP
t
+ 2 x
DQSCK.MAX
t
t
t
3.
= MIN (
nRP.nCK
DS
= + 293 ps, then
DH
t
HP
t
with differential data strobe enabled MR[bit10] = 0, is referenced from the input signal crossing at the
CK
with differential data strobe enabled MR[bit10] = 0, is referenced from the differential data strobe crosspoint to
t
CK
is the minimum of the absolute half period of the actual input clock; and
(ns)}, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For
QHS
Figure
Figure
+
= WR + RU{
t
V
CH.ABS
–
t
t
IH
IH.DC
t
WR
to derive the DRAM output timing
ERR(6-10PER).MIN
.
t
programmed to 4 clocks.
HP
,
t
4.
4.
LZ.DQ.MAX(DERATED)
level for a falling signal and from the differential data strobe crosspoint to the input signal crossing
t
CL.ABS
V
of 1315 ps into a DDR2–667 SDRAM, the DRAM provides
t
REF
DQSCK.MIN(DERATED)
t
RP
V
), where,
stabilizes. During the period before
TT
[ps] /
. component datasheet
= 400 ps + 272 ps = + 672 ps. Similarly,
t
CK.AVG
t
t
XP
CH.ABS
= 450 ps + 272 ps = + 722 ps. (Caution on the MIN/MAX usage!)
= 2 [nCK] means; if Power Down exit is registered at Tm, an Active command
t
CK.AVG
[ps] }, where WR is the value programmed in the EMR.
=
t
t
is the minimum of the actual instantaneous clock high time;
HZ
DQSCK.MIN
t
DAL
), or begins driving (
+
17
= 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks.
t
ERR.2PER(Min)
t
QH
t
. The value to be used for
–
HP
V
V
t
QH
t
IL.DC
IH.AC
ERR(6-10PER).MAX
t
is an input parameter but not an input specification parameter.
JIT.PER
of 1080 ps minimum.
t
t
QH
CK
level for a rising signal and
level for a rising signal and
.
value is; and the larger the valid data eye will be.}
V
refers to the application clock period. Example: For
,
t
REF
t
CK.AVG
JIT.CC
t
LZ
stabilizes, CKE = 0.2 x
) .
Small Outlined DDR2 SDRAM Modules
, etc.), as these are relative to the clock signal
t
‘ represents the actual
LZ.DQ
= – 400 ps – 293 ps = – 693 ps and
HYS64T128020EDL–[2.5/3S/3.7]–B
for DDR2–667 derates to
V
t
t
QH
QH
IL.AC
t
t
QHS
ERR(6-10per)
calculation is determined by the
of 975 ps minimum. 2) If the system
level to the differential data strobe
is the specification value under
V
V
IH.DC
IL.AC
V
V
il(DC)MAX
of the input clock. (output
DDQ
for a falling signal applied
for a falling signal applied
t
Internet Data Sheet
CK.AVG
t
ERR(6-10PER).MIN
is recognized as low.
V
and
IL.DC.MAX
of the input clock
t
LZ.DQ.MIN(DERATED)
t
t
t
JIT.PER
CL.ABS
RP
V
ih(DC)MIN
, if the result
V
and
,
IH.AC
is the
t
= – 272
JIT.CC
. See
level
,