HYS64T128020EDL-2.5-B QIMONDA [Qimonda AG], HYS64T128020EDL-2.5-B Datasheet - Page 22

• Manufacturer Part Number: HYS64T128020EDL-2.5-B
• Description: 200-Pin Small-Outlined DDR2 SDRAM Modules
• Manufacturer: QIMONDA [Qimonda AG]

12) MIN (
13) The
14) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C
15) 0 °C≤
16) 85 °C <
17) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device
18) The
19) The maximum limit for the
20) Minimum
21) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard active power-
22) WR must be programmed to fulfill the minimum requirement for the
3.3.3
This chapter describes the ODT AC electrical characteristics.
1) New units, “t
2) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when
3) ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
Rev. 1.12, 2007-10
10312006-I253-V1V0
Symbol
t
t
t
t
t
t
t
t
AOND
AON
AONPD
AOFD
AOF
AOFPD
ANPD
AXPD
be greater than the minimum specification limits for
(
parameters are verified by design and characterization, but not subject to production test.
and 95 °C.
performance (bus turnaround) degrades accordingly.
down mode” (MR, A12 = “0”) a fast power-down exit timing
power-down exit timing
up to the next integer value.
refers to the application clock period. WR refers to the WR parameter stored in the MRS.
under operation. Unit “
DDR2-533, “
be registered at
the ODT resistance is fully on. Both are measured from
2 clock cycles after the clock edge that registered a first ODT HIGH counting the actual input clock edges.
Both are measured from
ns (= 0.5 x 3 ns) after the second trailing clock edge counting from the clock edge that registered a first ODT LOW and by counting the
actual input clock edges.
t
HZ,
t
t
t
HZ
RPST
RRD
t
CL
T
,
CASE
T
,
t
RPST
timing parameter depends on the page size of the DRAM organization.
), or begins driving (
t
CASE
t
Parameter / Condition
ODT turn-on delay
ODT turn-on
ODT turn-on (Power-Down Modes)
ODT turn-off delay
ODT turn-off
ODT turn-off (Power-Down Modes)
ODT to Power Down Mode Entry Latency
ODT Power Down Exit Latency
CH
WTR
) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can
CK.AVG
t
≤ 85 °C.
CK
and
≤ 95 °C.
is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz.
” is used for both concepts. Example:
T
m
t
” and “
LZ
+ 2, even if (
ODT AC Electrical Characteristics
,
t
RPRE
n
t
CK
XARDS
n
t
AOFD
” represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2-400 and
CK
t
parameters are referenced to a specific voltage level, which specify when the device output is no longer driving
WPST
”, are introduced in DDR2-667 and DDR2-800. Unit “
t
t
DAL
, which is interpreted differently per speed bin. For DDR2-667/800, if
LZ,
has to be satisfied.
ODT AC Characteristics and Operating Conditions for DDR2-667 & DDR2-800
T
parameter is not a device limit. The device operates with a greater value for this parameter, but system
t
= WR + (
RPRE
m
+ 2 -
).
t
HZ
T
t
m
RP
and
) is 2 x
/
t
CK
t
LZ
). For each of the terms, if not already an integer, round to the next highest integer.
t
transitions occur in the same access time windows as valid data transitions.These
CK.AVG
t
CL
t
XP
and
t
= 2 [
AOND
+
t
t
t
XARD
CH
n
ERR.2PER(Min)
, which is interpreted differently per speed bin. For DDR2-667/800,
CK
).
Values
Min.
2
t
t
2.5
t
t
3
8
] means; if Power Down exit is registered at
AC.MIN
AC.MIN
AC.MIN
AC.MIN
22
can be used. In “low active power-down mode” (MR, A12 =”1”) a slow
t
WR
timing parameter, where
+ 2 ns
+ 2 ns
.
t
CK.AVG
Max.
2
t
2
2.5
t
2.5
—
—
AC.MAX
AC.MAX
t
CK +
t
Small Outlined DDR2 SDRAM Modules
” represents the actual
CK +
t
+ 0.7 ns
AC.MAX
+ 0.6 ns
HYS64T128020EDL–[2.5/3S/3.7]–B
t
AC.MAX
WR
+ 1 ns
t
MIN
CK(avg)
+ 1 ns
[cycles] =
= 3 ns is assumed,
T
m
, an Active command may
t
CK.AVG
Unit
n
ns
ns
n
ns
ns
n
n
Internet Data Sheet
t
WR
CK
CK
CK
CK
(ns)/
TABLE 16
of the input clock
t
CK
(ns) rounded
Note
1)
1)2)
1)
1)
1)3)
1)
1)
1)
t
AOFD
t
AOND
is 1.5
t
CK
is