HYS64T128020EDL-2.5-C QIMONDA [Qimonda AG], HYS64T128020EDL-2.5-C Datasheet - Page 4

• Manufacturer Part Number: HYS64T128020EDL-2.5-C
• Description: 200-Pin SO-DIMM DDR2 SDRAM Modules
• Manufacturer: QIMONDA [Qimonda AG]

1.2
The Qimonda HYS64T[128/256]020EDL-[25F/2.5/3/3S/3.7]-C
module family are small outline DIMM modules “SO-DIMMs”
with 30 mm height based on DDR2 technology. DIMMs are
available as non-ECC modules in 128M × 64 (1GB) and
256M × 64 (2 GB) organization and density, intended for
mounting into 200-pin connector sockets.
1) All Product Type numbers end with a place code, designating the silicon die revision. Example: HYS64T128020EDL–3.7–C, indicating Rev.
2) The Compliance Code is printed on the module label and describes the speed grade, for example “PC2–4200S–444–12–A0”, where 4200S
Rev. 1.0, 2007-03
11212006-D34H-5W6Z
Product Type
PC2–6400
HYS64T128020EDL–25F–C
HYS64T256020EDL–25F–C
PC2–6400
HYS64T128020EDL–2.5–C
HYS64T256020EDL–2.5–C
PC2–5300
HYS64T128020EDL–3–C
HYS64T256020EDL–3–C
PC2–5300
HYS64T128020EDL–3S–C
HYS64T256020EDL–3S–C
PC2–4200
HYS64T128020EDL–3.7–C
HYS64T256020EDL–3.7–C
“C” dies are used for DDR2 SDRAM components. For all Qimonda DDR2 module and component nomenclature see
sheet.
means Unbuffered SO-DIMM modules with 4.26 GB/sec Module Bandwidth and “444-12” means Column Address Strobe (CAS) latency
= 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4 using the latest JEDEC SPD Revision 1.2 and produced
on the Raw Card “A”.
1)
Description
Compliance Code
1 GB 2R×16 PC2–6400S–555–12–A0
2 GB 2R×8 PC2–6400S–555–12–F0
1 GB 2R×16 PC2–6400S–666–12–A0
2 GB 2R×8 PC2–6400S–666–12–F0
1 GB 2R×16 PC2–5300S–444–12–A0
2 GB 2R×8 PC2–5300S–444–12–F0
1 GB 2R×16 PC2–5300S–555–12–A0
2 GB 2R×8 PC2–5300S–555–12–F0
1 GB 2R×16 PC2–4200S–444–12–A0
2 GB 2R×8 PC2–4200S–444–12–F0
2)
4
Ordering Information for RoHS Compliant Products
The memory array is designed with 1-Gbit Double-Data-Rate-
Two (DDR2) Synchronous DRAMs. Decoupling capacitors
are mounted on the PCB board. The DIMMs feature serial
presence detect based on a serial E
2-pin I
configuration data and are write protected; the
128 bytes are available to the customer.
2
C protocol. The first 128 bytes are programmed with
HYS64T[128/256]020EDL-[25F/2.5/3/3S/3.7]-C
Description
2 Rank, Non-ECC
2 Rank, Non-ECC
2 Rank, Non-ECC
2 Rank, Non-ECC
2 Rank, Non-ECC
2 Rank, Non-ECC
2 Rank, Non-ECC
2 Rank, Non-ECC
2 Rank, Non-ECC
2 Rank, Non-ECC
SO-DIMM DDR2 SDRAM Module
2
PROM device using the
Internet Data Sheet
Chapter 6
SDRAM
Technology
1 Gbit (×16)
1 Gbit (×8)
1 Gbit (×16)
1 Gbit (×8)
1 Gbit (×16)
1 Gbit (×8)
1 Gbit (×16)
1 Gbit (×8)
1 Gbit (×16)
1 Gbit (×8)
TABLE 2
of this data
second